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From: Xiaowei Bao <xiaowei.bao@nxp.com>
To: Zhiqiang.Hou@nxp.com, Minghuan.Lian@nxp.com, mingkai.hu@nxp.com,
	bhelgaas@google.com, robh+dt@kernel.org, shawnguo@kernel.org,
	leoyang.li@nxp.com, kishon@ti.com, lorenzo.pieralisi@arm.com,
	roy.zang@nxp.com, amurray@thegoodpenguin.co.uk,
	jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
	andrew.murray@arm.com, linux-pci@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linuxppc-dev@lists.ozlabs.org
Cc: Xiaowei Bao <xiaowei.bao@nxp.com>
Subject: [PATCH v6 07/11] PCI: layerscape: Modify the way of getting capability with different PEX
Date: Sat, 14 Mar 2020 11:30:34 +0800
Message-ID: <20200314033038.24844-8-xiaowei.bao@nxp.com> (raw)
In-Reply-To: <20200314033038.24844-1-xiaowei.bao@nxp.com>

The different PCIe controller in one board may be have different
capability of MSI or MSIX, so change the way of getting the MSI
capability, make it more flexible.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
---
v2:
 - Remove the repeated assignment code.
v3:
 - Use ep_func msi_cap and msix_cap to decide the msi_capable and
   msix_capable of pci_epc_features struct.
v4:
 - No change.
v5:
 - No change.
v6:
 - No change.

 drivers/pci/controller/dwc/pci-layerscape-ep.c | 31 +++++++++++++++++++-------
 1 file changed, 23 insertions(+), 8 deletions(-)

diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
index 0691d9a..9601f9c 100644
--- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
+++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
@@ -22,6 +22,7 @@
 
 struct ls_pcie_ep {
 	struct dw_pcie		*pci;
+	struct pci_epc_features	*ls_epc;
 };
 
 #define to_ls_pcie_ep(x)	dev_get_drvdata((x)->dev)
@@ -40,26 +41,31 @@ static const struct of_device_id ls_pcie_ep_of_match[] = {
 	{ },
 };
 
-static const struct pci_epc_features ls_pcie_epc_features = {
-	.linkup_notifier = false,
-	.msi_capable = true,
-	.msix_capable = false,
-	.bar_fixed_64bit = (1 << BAR_2) | (1 << BAR_4),
-};
-
 static const struct pci_epc_features*
 ls_pcie_ep_get_features(struct dw_pcie_ep *ep)
 {
-	return &ls_pcie_epc_features;
+	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+	struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci);
+
+	return pcie->ls_epc;
 }
 
 static void ls_pcie_ep_init(struct dw_pcie_ep *ep)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+	struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci);
+	struct dw_pcie_ep_func *ep_func;
 	enum pci_barno bar;
 
+	ep_func = dw_pcie_ep_get_func_from_ep(ep, 0);
+	if (!ep_func)
+		return;
+
 	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
 		dw_pcie_ep_reset_bar(pci, bar);
+
+	pcie->ls_epc->msi_capable = ep_func->msi_cap ? true : false;
+	pcie->ls_epc->msix_capable = ep_func->msix_cap ? true : false;
 }
 
 static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
@@ -119,6 +125,7 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev)
 	struct device *dev = &pdev->dev;
 	struct dw_pcie *pci;
 	struct ls_pcie_ep *pcie;
+	struct pci_epc_features *ls_epc;
 	struct resource *dbi_base;
 	int ret;
 
@@ -130,6 +137,10 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev)
 	if (!pci)
 		return -ENOMEM;
 
+	ls_epc = devm_kzalloc(dev, sizeof(*ls_epc), GFP_KERNEL);
+	if (!ls_epc)
+		return -ENOMEM;
+
 	dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
 	pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
 	if (IS_ERR(pci->dbi_base))
@@ -140,6 +151,10 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev)
 	pci->ops = &ls_pcie_ep_ops;
 	pcie->pci = pci;
 
+	ls_epc->bar_fixed_64bit = (1 << BAR_2) | (1 << BAR_4),
+
+	pcie->ls_epc = ls_epc;
+
 	platform_set_drvdata(pdev, pcie);
 
 	ret = ls_add_pcie_ep(pcie, pdev);
-- 
2.9.5


  parent reply index

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-14  3:30 [PATCH v6 00/11] Add the multiple PF support for DWC and Layerscape Xiaowei Bao
2020-03-14  3:30 ` [PATCH v6 01/11] PCI: designware-ep: Add multiple PFs support for DWC Xiaowei Bao
2020-05-20 20:32   ` Rob Herring
2020-03-14  3:30 ` [PATCH v6 02/11] PCI: designware-ep: Add the doorbell mode of MSI-X in EP mode Xiaowei Bao
2020-03-14  3:30 ` [PATCH v6 03/11] PCI: designware-ep: Move the function of getting MSI capability forward Xiaowei Bao
2020-03-14  3:30 ` [PATCH v6 04/11] PCI: designware-ep: Modify MSI and MSIX CAP way of finding Xiaowei Bao
2020-05-20 20:45   ` Rob Herring
2020-03-14  3:30 ` [PATCH v6 05/11] dt-bindings: pci: layerscape-pci: Add compatible strings for ls1088a and ls2088a Xiaowei Bao
2020-03-14  3:30 ` [PATCH v6 06/11] PCI: layerscape: Fix some format issue of the code Xiaowei Bao
2020-03-14  3:30 ` Xiaowei Bao [this message]
2020-05-20 20:45   ` [PATCH v6 07/11] PCI: layerscape: Modify the way of getting capability with different PEX Rob Herring
2020-03-14  3:30 ` [PATCH v6 08/11] PCI: layerscape: Modify the MSIX to the doorbell mode Xiaowei Bao
2020-03-14  3:30 ` [PATCH v6 09/11] PCI: layerscape: Add EP mode support for ls1088a and ls2088a Xiaowei Bao
2020-05-20 20:50   ` Rob Herring
2020-03-14  3:30 ` [PATCH v6 10/11] arm64: dts: layerscape: Add PCIe EP node for ls1088a Xiaowei Bao
2020-03-14  3:30 ` [PATCH v6 11/11] misc: pci_endpoint_test: Add LS1088a in pci_device_id table Xiaowei Bao
2020-07-06 10:46 ` [PATCH v6 00/11] Add the multiple PF support for DWC and Layerscape Lorenzo Pieralisi
2020-07-07  2:10   ` Z.q. Hou

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