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From: Bjorn Helgaas <>
To: Vignesh Raghavendra <>
Cc: Kishon Vijay Abraham I <>,
	Lorenzo Pieralisi <>,
	Andrew Murray <>,,,, Marc Zyngier <>,
	Thomas Gleixner <>
Subject: Re: [PATCH v4] PCI: dwc: pci-dra7xx: Fix MSI IRQ handling
Date: Mon, 30 Mar 2020 11:37:03 -0500	[thread overview]
Message-ID: <> (raw)
In-Reply-To: <>

On Mon, Mar 30, 2020 at 11:29:52AM -0500, Bjorn Helgaas wrote:
> [+cc Marc, Thomas]
> On Fri, Mar 27, 2020 at 03:24:34PM +0530, Vignesh Raghavendra wrote:
> > Due an issue with PCIe wrapper around DWC PCIe IP on dra7xx, driver
> > needs to ensure that there are no pending MSI IRQ vector set (i.e
> > PCIE_MSI_INTR0_STATUS reads 0 at least once) before exiting IRQ handler.
> > Else, the dra7xx PCIe wrapper will not register new MSI IRQs even though
> > PCIE_MSI_INTR0_STATUS shows IRQs are pending.
> I'm not an IRQ guy (real IRQ guys CC'd), but I'm wondering if this is
> really a symptom of a problem in the generic DWC IRQ handling, not a
> problem in dra7xx itself.
> I thought it was sort of standard behavior that a device would not
> send a new MSI unless there was a transition from "no status bits set"
> to "at least one status bit set".  I'm looking at this text from the
> PCIe r5.0 spec, sec
>   If the Port is enabled for edge-triggered interrupt signaling using
>   MSI or MSI-X, an interrupt message must be sent every time the
>   logical AND of the following conditions transitions from FALSE to
>   TRUE:
>     - The associated vector is unmasked (not applicable if MSI does
>       not support PVM).
>     - The Hot-Plug Interrupt Enable bit in the Slot Control register
>       is set to 1b.
>     - At least one hot-plug event status bit in the Slot Status
>       register and its associated enable bit in the Slot Control
>       register are both set to 1b.
> and this related commit:

and this one:

  reply	other threads:[~2020-03-30 16:37 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-27  9:54 [PATCH v4] PCI: dwc: pci-dra7xx: Fix MSI IRQ handling Vignesh Raghavendra
2020-03-27 15:01 ` Lorenzo Pieralisi
2020-03-30 16:29 ` Bjorn Helgaas
2020-03-30 16:37   ` Bjorn Helgaas [this message]
2020-03-31 11:05     ` Vignesh Raghavendra
2020-03-30 21:12   ` Thomas Gleixner
2020-03-31 16:09     ` Bjorn Helgaas

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