From: Sean V Kelley <sean.v.kelley@linux.intel.com>
To: mj@ucw.cz, bhelgaas@google.com
Cc: linux-pci@vger.kernel.org, Sean V Kelley <sean.v.kelley@linux.intel.com>
Subject: [PATCH v3 0/2] pciutils: Add basic decode support for CXL
Date: Fri, 10 Apr 2020 16:24:38 -0700 [thread overview]
Message-ID: <20200410232440.668057-1-sean.v.kelley@linux.intel.com> (raw)
Changes since v2 [1]:
- Separate DVSEC capabilities from CXL and provide a means to identify.
(Bjorn Helgaas)
Changes since v1 [2]:
- Use consistent syntax to match other lspci capability output.
(Bjorn Helgaas)
[1] https://lore.kernel.org/linux-pci/20200409213019.335678-1-sean.v.kelley@linux.intel.com/
[2] https://lore.kernel.org/linux-pci/20200409183204.328057-1-sean.v.kelley@linux.intel.com/
This patch series adds support for basic lspci decode of Compute eXpress Link[3],
a new CPU interconnect building upon PCIe. As a foundation for the CXL
support it adds separate Designated Vendor-Specific Capability (DVSEC) defines
and a cap function so as to align with PCIe r5.0, sec 7.9.6.2 terms and
provide available details. It makes use of the Vendor ID so as to identify
a Flex Bus capable port for purposes of CXL support.
[3] https://www.computeexpresslink.org/
Sean V Kelley (2):
lspci: Add available DVSEC details
lspci: Add basic decode support for Compute eXpress Link
lib/header.h | 24 ++++
ls-ecaps.c | 73 +++++++++-
tests/cap-dvsec | 340 ++++++++++++++++++++++++++++++++++++++++++++
tests/cap-dvsec-cxl | 340 ++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 776 insertions(+), 1 deletion(-)
create mode 100644 tests/cap-dvsec
create mode 100644 tests/cap-dvsec-cxl
--
2.26.0
next reply other threads:[~2020-04-10 23:24 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-10 23:24 Sean V Kelley [this message]
2020-04-10 23:24 ` [PATCH v3 1/2] lspci: Add available DVSEC details Sean V Kelley
2020-04-10 23:24 ` [PATCH v3 2/2] lspci: Add basic decode support for Compute eXpress Link Sean V Kelley
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