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From: Sean V Kelley <>
Cc:, Sean V Kelley <>
Subject: [PATCH v4 0/2] pciutils: Add basic decode support for CXL DVSEC
Date: Mon, 13 Apr 2020 08:35:24 -0700	[thread overview]
Message-ID: <> (raw)

Changes since v3 [1]:

- Non-functional changes, subject and typo corrections

Changes since v2 [2]:

- Separate DVSEC capabilities from CXL and provide a means to identify.
(Bjorn Helgaas)

Changes since v1 [3]:

- Use consistent syntax to match other lspci capability output.
(Bjorn Helgaas)


This patch series adds support for basic lspci decode of Compute eXpress Link[4],
a new CPU interconnect building upon PCIe.  As a foundation for the CXL
support it adds separate Designated Vendor-Specific Capability (DVSEC) defines
and a cap function so as to align with PCIe r5.0, sec terms and
provide available details.  It makes use of the Vendor ID so as to identify
a Flex Bus capable port for purposes of CXL support.


Sean V Kelley (2):
  pciutils: Decode available DVSEC details
  pciutils: Decode Compute eXpress Link DVSEC

 lib/header.h        |  24 ++++
 ls-ecaps.c          |  73 +++++++++-
 tests/cap-dvsec     | 340 ++++++++++++++++++++++++++++++++++++++++++++
 tests/cap-dvsec-cxl | 340 ++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 776 insertions(+), 1 deletion(-)
 create mode 100644 tests/cap-dvsec
 create mode 100644 tests/cap-dvsec-cxl


             reply	other threads:[~2020-04-13 15:35 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-13 15:35 Sean V Kelley [this message]
2020-04-13 15:35 ` [PATCH v4 1/2] pciutils: Decode available DVSEC details Sean V Kelley
2020-04-13 15:35 ` [PATCH v4 2/2] pciutils: Decode Compute eXpress Link DVSEC Sean V Kelley
2020-04-14 20:37   ` Bjorn Helgaas
2020-04-14 21:01     ` Sean V Kelley

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