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From: Rob Herring <robh@kernel.org>
To: Ansuel Smith <ansuelsmth@gmail.com>
Cc: Andy Gross <agross@kernel.org>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Mark Rutland <mark.rutland@arm.com>,
	Stanimir Varbanov <svarbanov@mm-sol.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Andrew Murray <amurray@thegoodpenguin.co.uk>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 09/10] devicetree: bindings: pci: add ipq8064 rev 2 variant to qcom,pcie
Date: Tue, 14 Apr 2020 12:07:57 -0500	[thread overview]
Message-ID: <20200414170757.GA11622@bogus> (raw)
In-Reply-To: <20200402121148.1767-10-ansuelsmth@gmail.com>

On Thu, Apr 02, 2020 at 02:11:46PM +0200, Ansuel Smith wrote:
> Document qcom,pcie-ipq8064-v2 needed to use different phy_tx0_term_offset.
> In ipq8064 phy_tx0_term_offset is 7, in rev 2, ipq8065 and other SoC it's
> set to 0 by default.
> 
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> ---
>  .../devicetree/bindings/pci/qcom,pcie.txt     | 42 +++++++++++++++++++
>  1 file changed, 42 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
> index 6efcef040741..b699f126ea29 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
> @@ -5,6 +5,7 @@
>  	Value type: <stringlist>
>  	Definition: Value should contain
>  			- "qcom,pcie-ipq8064" for ipq8064
> +			- "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065
>  			- "qcom,pcie-apq8064" for apq8064
>  			- "qcom,pcie-apq8084" for apq8084
>  			- "qcom,pcie-msm8996" for msm8996 or apq8096
> @@ -295,6 +296,47 @@
>  		pinctrl-names = "default";
>  	};
>  
> +* Example for ipq8064 rev 2 or ipq8065

Just a new compatible string doesn't warrant a whole new example.

> +	pcie@1b500000 {
> +		compatible = "qcom,pcie-ipq8064-v2", "snps,dw-pcie";
> +		reg = <0x1b500000 0x1000
> +		       0x1b502000 0x80
> +		       0x1b600000 0x100
> +		       0x0ff00000 0x100000>;
> +		reg-names = "dbi", "elbi", "parf", "config";
> +		device_type = "pci";
> +		linux,pci-domain = <0>;
> +		bus-range = <0x00 0xff>;
> +		num-lanes = <1>;
> +		#address-cells = <3>;
> +		#size-cells = <2>;
> +		ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000   /* I/O */
> +			  0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
> +		interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
> +		interrupt-names = "msi";
> +		#interrupt-cells = <1>;
> +		interrupt-map-mask = <0 0 0 0x7>;
> +		interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> +				<0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
> +				<0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
> +				<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
> +		clocks = <&gcc PCIE_A_CLK>,
> +			 <&gcc PCIE_H_CLK>,
> +			 <&gcc PCIE_PHY_CLK>,
> +			 <&gcc PCIE_AUX_CLK>,
> +			 <&gcc PCIE_ALT_REF_CLK>;
> +		clock-names = "core", "iface", "phy", "aux", "ref";
> +		resets = <&gcc PCIE_ACLK_RESET>,
> +			 <&gcc PCIE_HCLK_RESET>,
> +			 <&gcc PCIE_POR_RESET>,
> +			 <&gcc PCIE_PCI_RESET>,
> +			 <&gcc PCIE_PHY_RESET>,
> +			 <&gcc PCIE_EXT_RESET>;
> +		reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
> +		pinctrl-0 = <&pcie_pins_default>;
> +		pinctrl-names = "default";
> +	};
> +
>  * Example for apq8084
>  	pcie0@fc520000 {
>  		compatible = "qcom,pcie-apq8084", "snps,dw-pcie";
> -- 
> 2.25.1
> 

  reply	other threads:[~2020-04-14 17:08 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-02 12:11 [PATCH v2 00/10] Multiple fixes in PCIe qcom driver Ansuel Smith
2020-04-02 12:11 ` [PATCH v2 01/10] PCIe: qcom: add missing ipq806x clocks in PCIe driver Ansuel Smith
2020-04-08  8:50   ` Stanimir Varbanov
2020-04-08 12:36     ` R: " ansuelsmth
2020-04-08 12:48       ` Stanimir Varbanov
2020-04-08 12:55         ` R: " ansuelsmth
2020-04-08 13:06           ` Stanimir Varbanov
2020-04-02 12:11 ` [PATCH v2 02/10] devicetree: bindings: pci: add missing clks to qcom,pcie Ansuel Smith
2020-04-02 12:11 ` [PATCH v2 03/10] PCIe: qcom: change duplicate PCI reset to phy reset Ansuel Smith
2020-04-02 12:11 ` [PATCH v2 04/10] PCIe: qcom: Fixed pcie_phy_clk branch issue Ansuel Smith
2020-04-02 12:11 ` [PATCH v2 05/10] PCIe: qcom: add missing reset for ipq806x Ansuel Smith
2020-04-02 12:11 ` [PATCH v2 06/10] devicetree: bindings: pci: add ext reset to qcom,pcie Ansuel Smith
2020-04-02 12:11 ` [PATCH v2 07/10] PCIe: qcom: fix init problem with missing PARF programming Ansuel Smith
2020-04-08  8:50   ` Stanimir Varbanov
2020-04-08 12:38     ` R: " ansuelsmth
2020-04-08 13:18       ` Stanimir Varbanov
2020-04-02 12:11 ` [PATCH v2 08/10] PCIe: qcom: add ipq8064 rev2 variant and set tx term offset Ansuel Smith
2020-04-02 12:11 ` [PATCH v2 09/10] devicetree: bindings: pci: add ipq8064 rev 2 variant to qcom,pcie Ansuel Smith
2020-04-14 17:07   ` Rob Herring [this message]
2020-04-02 12:11 ` [PATCH v2 10/10] PCIe: qcom: add Force GEN1 support Ansuel Smith
2020-04-03  9:01   ` Stanimir Varbanov
2020-04-14 17:09     ` Rob Herring
2020-04-03  9:01 ` [PATCH v2 00/10] Multiple fixes in PCIe qcom driver Stanimir Varbanov

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