[PATCH v5 0/2] pciutils: Add basic decode support for CXL DVSEC

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* [PATCH v5 0/2] pciutils: Add basic decode support for CXL DVSEC
@ 2020-04-15  0:47 Sean V Kelley
  2020-04-15  0:47 ` [PATCH v5 1/2] pciutils: Decode available DVSEC details Sean V Kelley
  2020-04-15  0:47 ` [PATCH v5 2/2] pciutils: Decode Compute eXpress Link DVSEC Sean V Kelley
  0 siblings, 2 replies; 8+ messages in thread
From: Sean V Kelley @ 2020-04-15  0:47 UTC (permalink / raw)
  To: mj, bhelgaas; +Cc: linux-pci, Sean V Kelley

Changes since v4 [1]:

- Describe CXL in terms of both the DVSEC Vendor ID and DVSEC ID.
(Bjorn Helgaas)

- Check the DVSEC Vendor ID first. Both the DVSEC Vendor ID and DVSEC ID must
match for CXL identification.
(Bjorn Helgaas)

- Renamed is_flexbus_cap() to is_cxl_cap() to more accurately reflect use.

- Added descriptions to the CXL support/control/status register bitfields.

[1] https://lore.kernel.org/linux-pci/20200413153526.805776-1-sean.v.kelley@linux.intel.com/

This patch series adds support for basic lspci decode of Compute eXpress Link[2],
a new CPU interconnect building upon PCIe. As a foundation for the CXL
support it adds separate Designated Vendor-Specific Capability (DVSEC) defines
and a cap function so as to align with PCIe r5.0, sec 7.9.6.2 terms and
provide available details. It makes use of the DVSEC Vendor ID and DVSEC ID so as
to identify a CXL capable device.

[2] https://www.computeexpresslink.org/

Sean V Kelley (2):
  pciutils: Decode available DVSEC details
  pciutils: Decode Compute eXpress Link DVSEC

 lib/header.h        |  24 ++++
 ls-ecaps.c          |  79 +++++++++-
 tests/cap-dvsec     | 340 ++++++++++++++++++++++++++++++++++++++++++++
 tests/cap-dvsec-cxl | 340 ++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 782 insertions(+), 1 deletion(-)
 create mode 100644 tests/cap-dvsec
 create mode 100644 tests/cap-dvsec-cxl

--
2.26.0


^ permalink raw reply	[flat|nested] 8+ messages in thread

* [PATCH v5 1/2] pciutils: Decode available DVSEC details
  2020-04-15  0:47 [PATCH v5 0/2] pciutils: Add basic decode support for CXL DVSEC Sean V Kelley
@ 2020-04-15  0:47 ` Sean V Kelley
  2020-04-15  0:47 ` [PATCH v5 2/2] pciutils: Decode Compute eXpress Link DVSEC Sean V Kelley
  1 sibling, 0 replies; 8+ messages in thread
From: Sean V Kelley @ 2020-04-15  0:47 UTC (permalink / raw)
  To: mj, bhelgaas; +Cc: linux-pci, Sean V Kelley

Instead of current generic 'unknown' output for DVSEC, decode details on
Vendor ID, Rev, etc.

Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Sean V Kelley <sean.v.kelley@linux.intel.com>
---
 lib/header.h    |   4 +
 ls-ecaps.c      |  25 +++-
 tests/cap-dvsec | 340 ++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 368 insertions(+), 1 deletion(-)
 create mode 100644 tests/cap-dvsec

diff --git a/lib/header.h b/lib/header.h
index bfdcc80..daeddeb 100644
--- a/lib/header.h
+++ b/lib/header.h
@@ -1042,6 +1042,10 @@
 #define PCI_EVNDR_HEADER	4	/* Vendor-Specific Header */
 #define PCI_EVNDR_REGISTERS	8	/* Vendor-Specific Registers */
 
+/* PCIe Designated Vendor-Specific Capability */
+#define PCI_DVSEC_HEADER1	4	/* Designated Vendor-Specific Header 1 */
+#define PCI_DVSEC_HEADER2	8	/* Designated Vendor-Specific Header 2 */
+
 /* Access Control Services */
 #define PCI_ACS_CAP		0x04	/* ACS Capability Register */
 #define PCI_ACS_CAP_VALID	0x0001	/* ACS Source Validation */
diff --git a/ls-ecaps.c b/ls-ecaps.c
index 0021734..b82d37e 100644
--- a/ls-ecaps.c
+++ b/ls-ecaps.c
@@ -634,6 +634,29 @@ cap_rclink(struct device *d, int where)
     }
 }
 
+static void
+cap_dvsec(struct device *d, int where)
+{
+  u32 hdr;
+
+  printf("Designated Vendor-Specific:\n");
+  if (!config_fetch(d, where + PCI_DVSEC_HEADER1, 8))
+    {
+      printf("<unreadable>\n");
+      return;
+    }
+
+  hdr = get_conf_long(d, where + PCI_DVSEC_HEADER1);
+  printf("\t\tDVSEC Vendor ID=%04x Rev=%d Len=%03x <?>\n",
+    BITS(hdr, 0, 16),
+    BITS(hdr, 16, 4),
+    BITS(hdr, 20, 12));
+
+  hdr = get_conf_long(d, where + PCI_DVSEC_HEADER2);
+  printf("\t\tDVSEC ID=%04x <?>\n",
+    BITS(hdr, 0, 16));
+}
+
 static void
 cap_evendor(struct device *d, int where)
 {
@@ -924,7 +947,7 @@ show_ext_caps(struct device *d, int type)
 	    printf("Readiness Time Reporting <?>\n");
 	    break;
 	  case PCI_EXT_CAP_ID_DVSEC:
-	    printf("Designated Vendor-Specific <?>\n");
+	    cap_dvsec(d, where);
 	    break;
 	  case PCI_EXT_CAP_ID_VF_REBAR:
 	    printf("VF Resizable BAR <?>\n");
diff --git a/tests/cap-dvsec b/tests/cap-dvsec
new file mode 100644
index 0000000..3b3558c
--- /dev/null
+++ b/tests/cap-dvsec
@@ -0,0 +1,340 @@
+4e:00.0 Unassigned class [ff00]: Intel Corporation Device 0d93
+        Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
+        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+        Interrupt: pin A routed to IRQ 255
+        NUMA node: 0
+        Region 0: Memory at b3100000 (32-bit, non-prefetchable) [disabled] [size=1M]
+        Region 2: I/O ports at a400 [disabled] [size=1K]
+        Region 4: Memory at b1000000 (32-bit, prefetchable) [disabled] [size=16M]
+        Capabilities: [40] Express (v2) Root Complex Integrated Endpoint, MSI 00
+                DevCap: MaxPayload 256 bytes, PhantFunc 0
+                        ExtTag+ RBE+ FLReset+
+                DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq-
+                        RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop- FLReset-
+                        MaxPayload 128 bytes, MaxReadReq 512 bytes
+                DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-
+                DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, NROPrPrP-, LTR+
+                         10BitTagComp-, 10BitTagReq-, OBFF Via WAKE#, ExtFmt+, EETLPPrefix+, MaxEETLPPrefixes 1
+                         EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
+                         FRS-
+                         AtomicOpsCap: 32bit+ 64bit+ 128bitCAS+
+                DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
+                         AtomicOpsCtl: ReqEn-
+        Capabilities: [80] MSI: Enable- Count=1/4 Maskable+ 64bit+
+                Address: 0000000000000000  Data: 0000
+                Masking: 00000000  Pending: 00000000
+        Capabilities: [a0] Power Management version 3
+                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+)
+                Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
+        Capabilities: [100 v1] Advanced Error Reporting
+                UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+                UEMsk:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+                UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
+                CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
+                CEMsk:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+
+                AERCap: First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn-
+                        MultHdrRecCap+ MultHdrRecEn- TLPPfxPres- HdrLogCap-
+                HeaderLog: 00000000 00000000 00000000 00000000
+        Capabilities: [200 v1] Multi-Function Virtual Channel <?>
+        Capabilities: [300 v1] Virtual Channel
+                Caps:   LPEVC=0 RefClk=100ns PATEntryBits=1
+                Arb:    Fixed- WRR32- WRR64- WRR128-
+                Ctrl:   ArbSelect=Fixed
+                Status: InProgress-
+                VC0:    Caps:   PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
+                        Arb:    Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
+                        Ctrl:   Enable+ ID=0 ArbSelect=Fixed TC/VC=ff
+                        Status: NegoPending- InProgress-
+        Capabilities: [550 v1] Multicast
+                McastCap: MaxGroups 64, WindowSz 1 (2 bytes)            McastCtl: NumGroups 1, Enable-
+                McastBAR: IndexPos 0, BaseAddr 0000000000000000
+                McastReceiveVec:      0000000000000000
+                McastBlockAllVec:     0000000000000000
+                McastBlockUntransVec: 0000000000000000
+        Capabilities: [588 v1] Latency Tolerance Reporting
+                Max snoop latency: 0ns
+                Max no snoop latency: 0ns
+        Capabilities: [5b0 v1] Transaction Processing Hints
+                Extended requester support
+                Steering table in TPH capability structure
+        Capabilities: [6e0 v1] Address Translation Service (ATS)
+                ATSCap: Invalidate Queue Depth: 00
+                ATSCtl: Enable-, Smallest Translation Unit: 00
+        Capabilities: [700 v1] Resizable BAR <?>
+        Capabilities: [714 v1] Secondary PCI Express
+                LnkCtl3: LnkEquIntrruptEn-, PerformEqu-
+                LaneErrStat: 0
+        Capabilities: [b20 v1] Page Request Interface (PRI)
+                PRICtl: Enable- Reset-
+                PRISta: RF- UPRGI- Stopped+
+                Page Request Capacity: 00000000, Page Request Allocation: 00000000
+        Capabilities: [b40 v1] Process Address Space ID (PASID)
+                PASIDCap: Exec+ Priv+, Max PASID Width: 14
+                PASIDCtl: Enable- Exec- Priv-
+        Capabilities: [b50 v1] Precision Time Measurement
+                PTMCap: Requester:- Responder:- Root:-
+                PTMClockGranularity: Unimplemented
+                PTMControl: Enabled:- RootSelected:-
+                PTMEffectiveGranularity: Unknown
+        Capabilities: [d00 v1] Vendor Specific Information: ID=0040 Rev=1 Len=04c <?>
+        Capabilities: [e00 v1] Designated Vendor Specific Extended Capability:
+                DVSEC Vendor ID=8086 Rev=0 Len=038 <?>
+                DVSEC ID=0000 <?>
+        Capabilities: [e38 v1] Device Serial Number 12-34-56-78-90-00-00-00
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+fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-- 
2.26.0


^ permalink raw reply related	[flat|nested] 8+ messages in thread

* [PATCH v5 2/2] pciutils: Decode Compute eXpress Link DVSEC
  2020-04-15  0:47 [PATCH v5 0/2] pciutils: Add basic decode support for CXL DVSEC Sean V Kelley
  2020-04-15  0:47 ` [PATCH v5 1/2] pciutils: Decode available DVSEC details Sean V Kelley
@ 2020-04-15  0:47 ` Sean V Kelley
  2020-04-18  8:36   ` Jay Fang
  1 sibling, 1 reply; 8+ messages in thread
From: Sean V Kelley @ 2020-04-15  0:47 UTC (permalink / raw)
  To: mj, bhelgaas; +Cc: linux-pci, Sean V Kelley

Compute eXpress Link[1] is a new CPU interconnect created with
workload accelerators in mind. The interconnect relies on PCIe
electrical and physical interconnect for communication via a Flex Bus
port which allows designs to choose between providing PCIe or CXL.

This patch introduces basic support for lspci decode of CXL and
builds upon the existing Designated Vendor-Specific support in
lspci through identification of a supporting CXL device using DVSEC
Vendor ID and DVSEC ID.

[1] https://www.computeexpresslink.org/

Signed-off-by: Sean V Kelley <sean.v.kelley@linux.intel.com>
---
 lib/header.h        |  20 +++
 ls-ecaps.c          |  56 +++++++-
 tests/cap-dvsec-cxl | 340 ++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 415 insertions(+), 1 deletion(-)
 create mode 100644 tests/cap-dvsec-cxl

diff --git a/lib/header.h b/lib/header.h
index daeddeb..e530a35 100644
--- a/lib/header.h
+++ b/lib/header.h
@@ -1045,6 +1045,26 @@
 /* PCIe Designated Vendor-Specific Capability */
 #define PCI_DVSEC_HEADER1	4	/* Designated Vendor-Specific Header 1 */
 #define PCI_DVSEC_HEADER2	8	/* Designated Vendor-Specific Header 2 */
+#define PCI_DVSEC_ID		0	/* Designated Vendor-Specific ID */
+
+/* PCIe CXL Designated Vendor-Specific Capabilities, Control, Status */
+#define PCI_CXL_CAP		0x0a	/* CXL Capability Register */
+#define  PCI_CXL_CAP_CACHE	0x0001	/* CXL.cache Protocol Support */
+#define  PCI_CXL_CAP_IO		0x0002	/* CXL.io Protocol Support */
+#define  PCI_CXL_CAP_MEM	0x0004	/* CXL.mem Protocol Support */
+#define  PCI_CXL_CAP_MEM_HWINIT	0x0008	/* CXL.mem Initalizes with HW/FW Support */
+#define  PCI_CXL_CAP_HDM_CNT(x)	(((x) & (3 << 4)) >> 4)	/* CXL Number of HDM ranges */
+#define  PCI_CXL_CAP_VIRAL	0x4000	/* CXL Viral Handling Support */
+#define PCI_CXL_CTRL		0x0c	/* CXL Control Register */
+#define  PCI_CXL_CTRL_CACHE	0x0001	/* CXL.cache Protocol Enable */
+#define  PCI_CXL_CTRL_IO	0x0002	/* CXL.io Protocol Enable */
+#define  PCI_CXL_CTRL_MEM	0x0004	/* CXL.mem Protocol Enable */
+#define  PCI_CXL_CTRL_CACHE_SF_COV(x)	(((x) & (0x1f << 3)) >> 3) /* Snoop Filter Coverage */
+#define  PCI_CXL_CTRL_CACHE_SF_GRAN(x)	(((x) & (0x7 << 8)) >> 8) /* Snoop Filter Granularity */
+#define  PCI_CXL_CTRL_CACHE_CLN	0x0800	/* CXL.cache Performance Hint on Clean Evictions */
+#define  PCI_CXL_CTRL_VIRAL	0x4000	/* CXL Viral Handling Enable */
+#define PCI_CXL_STATUS		0x0e	/* CXL Status Register */
+#define  PCI_CXL_STATUS_VIRAL	0x4000	/* CXL Viral Handling Status */
 
 /* Access Control Services */
 #define PCI_ACS_CAP		0x04	/* ACS Capability Register */
diff --git a/ls-ecaps.c b/ls-ecaps.c
index b82d37e..4e6e63f 100644
--- a/ls-ecaps.c
+++ b/ls-ecaps.c
@@ -634,6 +634,57 @@ cap_rclink(struct device *d, int where)
     }
 }
 
+static void
+cap_cxl(struct device *d, int where)
+{
+  u16 l;
+
+  printf("CXL Designated Vendor-Specific:\n");
+  if (verbose < 2)
+    return;
+
+  if (!config_fetch(d, where + PCI_CXL_CAP, 12))
+    return;
+
+  l = get_conf_word(d, where + PCI_CXL_CAP);
+  printf("\t\tCXLCap:\tCache%c IO%c Mem%c Mem HW Init%c HDMCount %d Viral%c\n",
+    FLAG(l, PCI_CXL_CAP_CACHE), FLAG(l, PCI_CXL_CAP_IO), FLAG(l, PCI_CXL_CAP_MEM),
+    FLAG(l, PCI_CXL_CAP_MEM_HWINIT), PCI_CXL_CAP_HDM_CNT(l), FLAG(l, PCI_CXL_CAP_VIRAL));
+
+  l = get_conf_word(d, where + PCI_CXL_CTRL);
+  printf("\t\tCXLCtl:\tCache%c IO%c Mem%c Cache SF Cov %d Cache SF Gran %d Cache Clean%c Viral%c\n",
+    FLAG(l, PCI_CXL_CTRL_CACHE), FLAG(l, PCI_CXL_CTRL_IO), FLAG(l, PCI_CXL_CTRL_MEM),
+    PCI_CXL_CTRL_CACHE_SF_COV(l), PCI_CXL_CTRL_CACHE_SF_GRAN(l), FLAG(l, PCI_CXL_CTRL_CACHE_CLN),
+    FLAG(l, PCI_CXL_CTRL_VIRAL));
+
+  l = get_conf_word(d, where + PCI_CXL_STATUS);
+  printf("\t\tCXLSta:\tViral%c\n", FLAG(l, PCI_CXL_STATUS_VIRAL));
+}
+
+static int
+is_cxl_cap(struct device *d, int where)
+{
+  u32 hdr;
+  u16 w;
+
+  if (!config_fetch(d, where + PCI_DVSEC_HEADER1, 8))
+    return 0;
+
+  /* Check for supported Vendor */
+  hdr = get_conf_long(d, where + PCI_DVSEC_HEADER1);
+  w = BITS(hdr, 0, 16);
+  if (w != PCI_VENDOR_ID_INTEL)
+    return 0;
+
+  /* Check for Designated Vendor-Specific ID */
+  hdr = get_conf_long(d, where + PCI_DVSEC_HEADER2);
+  w = BITS(hdr, 0, 16);
+  if (w == PCI_DVSEC_ID)
+    return 1;
+
+  return 0;
+}
+
 static void
 cap_dvsec(struct device *d, int where)
 {
@@ -947,7 +998,10 @@ show_ext_caps(struct device *d, int type)
 	    printf("Readiness Time Reporting <?>\n");
 	    break;
 	  case PCI_EXT_CAP_ID_DVSEC:
-	    cap_dvsec(d, where);
+	    if (is_cxl_cap(d, where))
+	      cap_cxl(d, where);
+	    else
+	      cap_dvsec(d, where);
 	    break;
 	  case PCI_EXT_CAP_ID_VF_REBAR:
 	    printf("VF Resizable BAR <?>\n");
diff --git a/tests/cap-dvsec-cxl b/tests/cap-dvsec-cxl
new file mode 100644
index 0000000..e5d2745
--- /dev/null
+++ b/tests/cap-dvsec-cxl
@@ -0,0 +1,340 @@
+6b:00.0 Unassigned class [ff00]: Intel Corporation Device 0d93
+        Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
+        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+        Interrupt: pin A routed to IRQ 255
+        NUMA node: 0
+        Region 0: Memory at b3100000 (32-bit, non-prefetchable) [disabled] [size=1M]
+        Region 2: I/O ports at a400 [disabled] [size=1K]
+        Region 4: Memory at b1000000 (32-bit, prefetchable) [disabled] [size=16M]
+        Capabilities: [40] Express (v2) Root Complex Integrated Endpoint, MSI 00
+                DevCap: MaxPayload 256 bytes, PhantFunc 0
+                        ExtTag+ RBE+ FLReset+
+                DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq+
+                        RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop- FLReset-
+                        MaxPayload 128 bytes, MaxReadReq 512 bytes
+                DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-
+                DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, NROPrPrP-, LTR+
+                         10BitTagComp-, 10BitTagReq-, OBFF Via WAKE#, ExtFmt+, EETLPPrefix+, MaxEETLPPrefixes 1
+                         EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
+                         FRS-
+                         AtomicOpsCap: 32bit+ 64bit+ 128bitCAS+
+                DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
+                         AtomicOpsCtl: ReqEn-
+        Capabilities: [80] MSI: Enable- Count=1/4 Maskable+ 64bit+
+                Address: 0000000000000000  Data: 0000
+                Masking: 00000000  Pending: 00000000
+        Capabilities: [a0] Power Management version 3
+                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+)
+                Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
+        Capabilities: [100 v1] Advanced Error Reporting
+                UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+                UEMsk:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol-
+                UESvrt: DLP+ SDES- TLP+ FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
+                CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
+                CEMsk:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+
+                AERCap: First Error Pointer: 00, ECRCGenCap+ ECRCGenEn+ ECRCChkCap+ ECRCChkEn+
+                        MultHdrRecCap+ MultHdrRecEn- TLPPfxPres- HdrLogCap-
+                HeaderLog: 00000000 00000000 00000000 00000000
+        Capabilities: [200 v1] Multi-Function Virtual Channel <?>
+        Capabilities: [300 v1] Virtual Channel
+                Caps:   LPEVC=0 RefClk=100ns PATEntryBits=1
+                Arb:    Fixed- WRR32- WRR64- WRR128-
+                Ctrl:   ArbSelect=Fixed
+                Status: InProgress-
+                VC0:    Caps:   PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
+                        Arb:    Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
+                        Ctrl:   Enable+ ID=0 ArbSelect=Fixed TC/VC=ff
+                        Status: NegoPending- InProgress-
+        Capabilities: [550 v1] Multicast
+                McastCap: MaxGroups 64, WindowSz 1 (2 bytes)            McastCtl: NumGroups 1, Enable-
+                McastBAR: IndexPos 0, BaseAddr 0000000000000000
+                McastReceiveVec:      0000000000000000
+                McastBlockAllVec:     0000000000000000
+                McastBlockUntransVec: 0000000000000000
+        Capabilities: [588 v1] Latency Tolerance Reporting
+                Max snoop latency: 0ns
+                Max no snoop latency: 0ns
+        Capabilities: [5b0 v1] Transaction Processing Hints
+                Extended requester support
+                Steering table in TPH capability structure
+        Capabilities: [6e0 v1] Address Translation Service (ATS)
+                ATSCap: Invalidate Queue Depth: 00
+                ATSCtl: Enable-, Smallest Translation Unit: 00
+        Capabilities: [700 v1] Resizable BAR <?>
+        Capabilities: [714 v1] Secondary PCI Express
+                LnkCtl3: LnkEquIntrruptEn-, PerformEqu-
+                LaneErrStat: 0
+        Capabilities: [b20 v1] Page Request Interface (PRI)
+                PRICtl: Enable- Reset-
+                PRISta: RF- UPRGI- Stopped+
+                Page Request Capacity: 00000000, Page Request Allocation: 00000000
+        Capabilities: [b40 v1] Process Address Space ID (PASID)
+                PASIDCap: Exec+ Priv+, Max PASID Width: 14
+                PASIDCtl: Enable- Exec- Priv-
+        Capabilities: [b50 v1] Precision Time Measurement
+                PTMCap: Requester:- Responder:- Root:-
+                PTMClockGranularity: Unimplemented
+                PTMControl: Enabled:- RootSelected:-
+                PTMEffectiveGranularity: Unknown
+        Capabilities: [d00 v1] Vendor Specific Information: ID=0040 Rev=1 Len=04c <?>
+        Capabilities: [e00 v1] CXL Designated Vendor-Specific:
+                CXLCap: Cache+ IO+ Mem+ Mem HW Init+ HDMCount 1 Viral-
+                CXLCtl: Cache+ IO+ Mem- Cache SF Cov 0 Cache SF Gran 0 Cache Clean- Viral-
+                CXLSta: Viral-
+        Capabilities: [e38 v1] Device Serial Number 12-34-56-78-90-00-00-00
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-- 
2.26.0


^ permalink raw reply related	[flat|nested] 8+ messages in thread

* Re: [PATCH v5 2/2] pciutils: Decode Compute eXpress Link DVSEC
  2020-04-15  0:47 ` [PATCH v5 2/2] pciutils: Decode Compute eXpress Link DVSEC Sean V Kelley
@ 2020-04-18  8:36   ` Jay Fang
  2020-04-20 16:21     ` Sean V Kelley
  0 siblings, 1 reply; 8+ messages in thread
From: Jay Fang @ 2020-04-18  8:36 UTC (permalink / raw)
  To: Sean V Kelley, mj, bhelgaas; +Cc: linux-pci, huangdaode

On 2020/4/15 8:47, Sean V Kelley wrote:

> 
> [1] https://www.computeexpresslink.org/
> 
> Signed-off-by: Sean V Kelley <sean.v.kelley@linux.intel.com>
> ---
>  lib/header.h        |  20 +++

> +
> +static int
> +is_cxl_cap(struct device *d, int where)
> +{
> +  u32 hdr;
> +  u16 w;
> +
> +  if (!config_fetch(d, where + PCI_DVSEC_HEADER1, 8))
> +    return 0;
> +
> +  /* Check for supported Vendor */
> +  hdr = get_conf_long(d, where + PCI_DVSEC_HEADER1);
> +  w = BITS(hdr, 0, 16);
> +  if (w != PCI_VENDOR_ID_INTEL)
I don't think here checking is quite right. Does only Intel support CXL?
Other Vendors should also be considered.

Thanks
> +    return 0;
> +
> +  /* Check for Designated Vendor-Specific ID */
> +  hdr = get_conf_long(d, where + PCI_DVSEC_HEADER2);
> +  w = BITS(hdr, 0, 16);
> +  if (w == PCI_DVSEC_ID)
> +    return 1;
> +
> +  return 0;
> +}
> +
>  static void
>  cap_dvsec(struct device *d, int where)
>  {
> @@ -947,7 +998,10 @@ show_ext_caps(struct device *d, int type)
>  	    printf("Readiness Time Reporting <?>\n");
>  	    break;
>  	  case PCI_EXT_CAP_ID_DVSEC:
> -	    cap_dvsec(d, where);
> +	    if (is_cxl_cap(d, where))
> +	      cap_cxl(d, where);
> +	    else
> +	      cap_dvsec(d, where);
>  	    break;
>  	  case PCI_EXT_CAP_ID_VF_REBAR:
>  	    printf("VF Resizable BAR <?>\n");
> diff --git a/tests/cap-dvsec-cxl b/tests/cap-dvsec-cxl
> new file mode 100644
> index 0000000..e5d2745
> --- /dev/null
> +++ b/tests/cap-dvsec-cxl
> @@ -0,0 +1,340 @@
> +6b:00.0 Unassigned class [ff00]: Intel Corporation Device 0d93
> +        Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-


^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH v5 2/2] pciutils: Decode Compute eXpress Link DVSEC
  2020-04-18  8:36   ` Jay Fang
@ 2020-04-20 16:21     ` Sean V Kelley
  2020-04-20 17:47       ` Bjorn Helgaas
  0 siblings, 1 reply; 8+ messages in thread
From: Sean V Kelley @ 2020-04-20 16:21 UTC (permalink / raw)
  To: Jay Fang; +Cc: mj, bhelgaas, linux-pci, huangdaode

Hi Jay,

Thank you for reviewing.  My comments below:

On 18 Apr 2020, at 1:36, Jay Fang wrote:

> On 2020/4/15 8:47, Sean V Kelley wrote:
>
>>
>> [1] https://www.computeexpresslink.org/
>>
>> Signed-off-by: Sean V Kelley <sean.v.kelley@linux.intel.com>
>> ---
>>  lib/header.h        |  20 +++
>
>> +
>> +static int
>> +is_cxl_cap(struct device *d, int where)
>> +{
>> +  u32 hdr;
>> +  u16 w;
>> +
>> +  if (!config_fetch(d, where + PCI_DVSEC_HEADER1, 8))
>> +    return 0;
>> +
>> +  /* Check for supported Vendor */
>> +  hdr = get_conf_long(d, where + PCI_DVSEC_HEADER1);
>> +  w = BITS(hdr, 0, 16);
>> +  if (w != PCI_VENDOR_ID_INTEL)
> I don't think here checking is quite right. Does only Intel support 
> CXL?
> Other Vendors should also be considered.

In the absence of currently available hardware, I was attempting to 
limit false positive noise.  I’m happy to avoid the check on the 
vendor if there were to exist a definitive supported list.  Bjorn 
suggested that I check for vendor ID with DVSEC ID for now.  As hardware 
enters the market, I can surely revise this with an update when the CXL 
group publishes a list.

Best regards,

Sean


>
> Thanks
>> +    return 0;
>> +
>> +  /* Check for Designated Vendor-Specific ID */
>> +  hdr = get_conf_long(d, where + PCI_DVSEC_HEADER2);
>> +  w = BITS(hdr, 0, 16);
>> +  if (w == PCI_DVSEC_ID)
>> +    return 1;
>> +
>> +  return 0;
>> +}
>> +
>>  static void
>>  cap_dvsec(struct device *d, int where)
>>  {
>> @@ -947,7 +998,10 @@ show_ext_caps(struct device *d, int type)
>>  	    printf("Readiness Time Reporting <?>\n");
>>  	    break;
>>  	  case PCI_EXT_CAP_ID_DVSEC:
>> -	    cap_dvsec(d, where);
>> +	    if (is_cxl_cap(d, where))
>> +	      cap_cxl(d, where);
>> +	    else
>> +	      cap_dvsec(d, where);
>>  	    break;
>>  	  case PCI_EXT_CAP_ID_VF_REBAR:
>>  	    printf("VF Resizable BAR <?>\n");
>> diff --git a/tests/cap-dvsec-cxl b/tests/cap-dvsec-cxl
>> new file mode 100644
>> index 0000000..e5d2745
>> --- /dev/null
>> +++ b/tests/cap-dvsec-cxl
>> @@ -0,0 +1,340 @@
>> +6b:00.0 Unassigned class [ff00]: Intel Corporation Device 0d93
>> +        Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- 
>> ParErr+ Stepping- SERR+ FastB2B- DisINTx-

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH v5 2/2] pciutils: Decode Compute eXpress Link DVSEC
  2020-04-20 16:21     ` Sean V Kelley
@ 2020-04-20 17:47       ` Bjorn Helgaas
  2020-04-20 17:54         ` Sean V Kelley
  2020-04-27  3:22         ` Jay Fang
  0 siblings, 2 replies; 8+ messages in thread
From: Bjorn Helgaas @ 2020-04-20 17:47 UTC (permalink / raw)
  To: Sean V Kelley; +Cc: Jay Fang, mj, linux-pci, huangdaode

Hi Jay, thanks for taking a look at this!

On Mon, Apr 20, 2020 at 09:21:27AM -0700, Sean V Kelley wrote:
> On 18 Apr 2020, at 1:36, Jay Fang wrote:
> > On 2020/4/15 8:47, Sean V Kelley wrote:
> > > 
> > > [1] https://www.computeexpresslink.org/
> > > 
> > > Signed-off-by: Sean V Kelley <sean.v.kelley@linux.intel.com>
> > > ---
> > >  lib/header.h        |  20 +++
> > 
> > > +
> > > +static int
> > > +is_cxl_cap(struct device *d, int where)
> > > +{
> > > +  u32 hdr;
> > > +  u16 w;
> > > +
> > > +  if (!config_fetch(d, where + PCI_DVSEC_HEADER1, 8))
> > > +    return 0;
> > > +
> > > +  /* Check for supported Vendor */
> > > +  hdr = get_conf_long(d, where + PCI_DVSEC_HEADER1);
> > > +  w = BITS(hdr, 0, 16);
> > > +  if (w != PCI_VENDOR_ID_INTEL)
> >
> > I don't think here checking is quite right. Does only Intel support CXL?
> > Other Vendors should also be considered.
> 
> In the absence of currently available hardware, I was attempting to limit
> false positive noise.  I’m happy to avoid the check on the vendor if there
> were to exist a definitive supported list.  Bjorn suggested that I check for
> vendor ID with DVSEC ID for now.  As hardware enters the market, I can
> surely revise this with an update when the CXL group publishes a list.

The Vendor ID check cannot be avoided.  Vendor IDs are allocated by
the PCI-SIG, but the DVSEC ID is vendor-defined so there cannot be a
global "CXL capability" DVSEC ID.

CXL *could* work through the PCI-SIG and define a new CXL Extended
Capability that could make this generic.  But apparently they've
chosen to use the DVSEC mechanism instead.

> > > +  /* Check for Designated Vendor-Specific ID */
> > > +  hdr = get_conf_long(d, where + PCI_DVSEC_HEADER2);
> > > +  w = BITS(hdr, 0, 16);
> > > +  if (w == PCI_DVSEC_ID)

However, this is slightly wrong.  The name "PCI_DVSEC_ID" implies that
there can only be one DVSEC ID and it is vendor-independent, but
neither is true.

This value is allocated by Intel, so we must check for the Intel
Vendor ID first.  And Intel may define several DVSEC capabilities for
different purposes, so the name should also mention CXL.

So this should be "PCI_DVSEC_INTEL_CXL" or something similar.

But that doesn't mean other vendors need to define their own DVSEC
IDs for CXL.  The spec (PCIe r5.0, sec 7.9.6) says:

  [The DVSEC Capability] allows PCI Express component vendors to use
  the Extended Capability mechanism to expose vendor-specific
  registers that can be present in components by a variety of
  vendors.

Any vendor that implements this CXL DVSEC the same way Intel does can
tag it with PCI_VENDOR_ID_INTEL and PCI_DVSEC_INTEL_CXL.

Note that there are two types of vendor-specific capabilities:

  1) Vendor-Specific Extended Capability (VSEC).  The structure and
  definition are defined by the *Function* Vendor ID (from offset 0 in
  config space) and the VSEC ID in the capability.

  2) Designated Vendor-Specific Extended Capability (DVSEC).  The
  structure and definition are defined by the *DVSEC* Vendor ID (from
  the DVSEC capability, *not* the vendor of the Function) and the
  DVSEC ID in the capability.

This CXL capability is the latter, of course.

Bjorn

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH v5 2/2] pciutils: Decode Compute eXpress Link DVSEC
  2020-04-20 17:47       ` Bjorn Helgaas
@ 2020-04-20 17:54         ` Sean V Kelley
  2020-04-27  3:22         ` Jay Fang
  1 sibling, 0 replies; 8+ messages in thread
From: Sean V Kelley @ 2020-04-20 17:54 UTC (permalink / raw)
  To: Bjorn Helgaas; +Cc: Jay Fang, mj, linux-pci, huangdaode

On 20 Apr 2020, at 10:47, Bjorn Helgaas wrote:

> Hi Jay, thanks for taking a look at this!
>
> On Mon, Apr 20, 2020 at 09:21:27AM -0700, Sean V Kelley wrote:
>> On 18 Apr 2020, at 1:36, Jay Fang wrote:
>>> On 2020/4/15 8:47, Sean V Kelley wrote:
>>>>
>>>> [1] https://www.computeexpresslink.org/
>>>>
>>>> Signed-off-by: Sean V Kelley <sean.v.kelley@linux.intel.com>
>>>> ---
>>>>  lib/header.h        |  20 +++
>>>
>>>> +
>>>> +static int
>>>> +is_cxl_cap(struct device *d, int where)
>>>> +{
>>>> +  u32 hdr;
>>>> +  u16 w;
>>>> +
>>>> +  if (!config_fetch(d, where + PCI_DVSEC_HEADER1, 8))
>>>> +    return 0;
>>>> +
>>>> +  /* Check for supported Vendor */
>>>> +  hdr = get_conf_long(d, where + PCI_DVSEC_HEADER1);
>>>> +  w = BITS(hdr, 0, 16);
>>>> +  if (w != PCI_VENDOR_ID_INTEL)
>>>
>>> I don't think here checking is quite right. Does only Intel support 
>>> CXL?
>>> Other Vendors should also be considered.
>>
>> In the absence of currently available hardware, I was attempting to 
>> limit
>> false positive noise.  I’m happy to avoid the check on the vendor 
>> if there
>> were to exist a definitive supported list.  Bjorn suggested that I 
>> check for
>> vendor ID with DVSEC ID for now.  As hardware enters the market, I 
>> can
>> surely revise this with an update when the CXL group publishes a 
>> list.
>
> The Vendor ID check cannot be avoided.  Vendor IDs are allocated by
> the PCI-SIG, but the DVSEC ID is vendor-defined so there cannot be a
> global "CXL capability" DVSEC ID.
>
> CXL *could* work through the PCI-SIG and define a new CXL Extended
> Capability that could make this generic.  But apparently they've
> chosen to use the DVSEC mechanism instead.
>
>>>> +  /* Check for Designated Vendor-Specific ID */
>>>> +  hdr = get_conf_long(d, where + PCI_DVSEC_HEADER2);
>>>> +  w = BITS(hdr, 0, 16);
>>>> +  if (w == PCI_DVSEC_ID)
>
> However, this is slightly wrong.  The name "PCI_DVSEC_ID" implies that
> there can only be one DVSEC ID and it is vendor-independent, but
> neither is true.
>
> This value is allocated by Intel, so we must check for the Intel
> Vendor ID first.  And Intel may define several DVSEC capabilities for
> different purposes, so the name should also mention CXL.
>
> So this should be "PCI_DVSEC_INTEL_CXL" or something similar.
>
> But that doesn't mean other vendors need to define their own DVSEC
> IDs for CXL.  The spec (PCIe r5.0, sec 7.9.6) says:
>
>   [The DVSEC Capability] allows PCI Express component vendors to use
>   the Extended Capability mechanism to expose vendor-specific
>   registers that can be present in components by a variety of
>   vendors.
>
> Any vendor that implements this CXL DVSEC the same way Intel does can
> tag it with PCI_VENDOR_ID_INTEL and PCI_DVSEC_INTEL_CXL.

Good point.  I will revise.

Thanks,

Sean

>
> Note that there are two types of vendor-specific capabilities:
>
>   1) Vendor-Specific Extended Capability (VSEC).  The structure and
>   definition are defined by the *Function* Vendor ID (from offset 0 in
>   config space) and the VSEC ID in the capability.
>
>   2) Designated Vendor-Specific Extended Capability (DVSEC).  The
>   structure and definition are defined by the *DVSEC* Vendor ID (from
>   the DVSEC capability, *not* the vendor of the Function) and the
>   DVSEC ID in the capability.
>
> This CXL capability is the latter, of course.
>
> Bjorn

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH v5 2/2] pciutils: Decode Compute eXpress Link DVSEC
  2020-04-20 17:47       ` Bjorn Helgaas
  2020-04-20 17:54         ` Sean V Kelley
@ 2020-04-27  3:22         ` Jay Fang
  1 sibling, 0 replies; 8+ messages in thread
From: Jay Fang @ 2020-04-27  3:22 UTC (permalink / raw)
  To: Bjorn Helgaas, Sean V Kelley; +Cc: mj, linux-pci, huangdaode

Got it.
Bjorn, thanks.

Jay

On 2020/4/21 1:47, Bjorn Helgaas wrote:
> Hi Jay, thanks for taking a look at this!
> 
> On Mon, Apr 20, 2020 at 09:21:27AM -0700, Sean V Kelley wrote:
>> On 18 Apr 2020, at 1:36, Jay Fang wrote:
>>> On 2020/4/15 8:47, Sean V Kelley wrote:
>>>>
>>>> [1] https://www.computeexpresslink.org/
>>>>
>>>> Signed-off-by: Sean V Kelley <sean.v.kelley@linux.intel.com>
>>>> ---
>>>>  lib/header.h        |  20 +++
>>>
>>>> +
>>>> +static int
>>>> +is_cxl_cap(struct device *d, int where)
>>>> +{
>>>> +  u32 hdr;
>>>> +  u16 w;
>>>> +
>>>> +  if (!config_fetch(d, where + PCI_DVSEC_HEADER1, 8))
>>>> +    return 0;
>>>> +
>>>> +  /* Check for supported Vendor */
>>>> +  hdr = get_conf_long(d, where + PCI_DVSEC_HEADER1);
>>>> +  w = BITS(hdr, 0, 16);
>>>> +  if (w != PCI_VENDOR_ID_INTEL)
>>>
>>> I don't think here checking is quite right. Does only Intel support CXL?
>>> Other Vendors should also be considered.
>>
>> In the absence of currently available hardware, I was attempting to limit
>> false positive noise.  I’m happy to avoid the check on the vendor if there
>> were to exist a definitive supported list.  Bjorn suggested that I check for
>> vendor ID with DVSEC ID for now.  As hardware enters the market, I can
>> surely revise this with an update when the CXL group publishes a list.
> 
> The Vendor ID check cannot be avoided.  Vendor IDs are allocated by
> the PCI-SIG, but the DVSEC ID is vendor-defined so there cannot be a
> global "CXL capability" DVSEC ID.
> 
> CXL *could* work through the PCI-SIG and define a new CXL Extended
> Capability that could make this generic.  But apparently they've
> chosen to use the DVSEC mechanism instead.
> 
>>>> +  /* Check for Designated Vendor-Specific ID */
>>>> +  hdr = get_conf_long(d, where + PCI_DVSEC_HEADER2);
>>>> +  w = BITS(hdr, 0, 16);
>>>> +  if (w == PCI_DVSEC_ID)
> 
> However, this is slightly wrong.  The name "PCI_DVSEC_ID" implies that
> there can only be one DVSEC ID and it is vendor-independent, but
> neither is true.
> 
> This value is allocated by Intel, so we must check for the Intel
> Vendor ID first.  And Intel may define several DVSEC capabilities for
> different purposes, so the name should also mention CXL.
> 
> So this should be "PCI_DVSEC_INTEL_CXL" or something similar.
> 
> But that doesn't mean other vendors need to define their own DVSEC
> IDs for CXL.  The spec (PCIe r5.0, sec 7.9.6) says:
> 
>   [The DVSEC Capability] allows PCI Express component vendors to use
>   the Extended Capability mechanism to expose vendor-specific
>   registers that can be present in components by a variety of
>   vendors.
> 
> Any vendor that implements this CXL DVSEC the same way Intel does can
> tag it with PCI_VENDOR_ID_INTEL and PCI_DVSEC_INTEL_CXL.
> 
> Note that there are two types of vendor-specific capabilities:
> 
>   1) Vendor-Specific Extended Capability (VSEC).  The structure and
>   definition are defined by the *Function* Vendor ID (from offset 0 in
>   config space) and the VSEC ID in the capability.
> 
>   2) Designated Vendor-Specific Extended Capability (DVSEC).  The
>   structure and definition are defined by the *DVSEC* Vendor ID (from
>   the DVSEC capability, *not* the vendor of the Function) and the
>   DVSEC ID in the capability.
> 
> This CXL capability is the latter, of course.
> 
> Bjorn
> 
> .
> 


^ permalink raw reply	[flat|nested] 8+ messages in thread

end of thread, other threads:[~2020-04-27  3:22 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-04-15  0:47 [PATCH v5 0/2] pciutils: Add basic decode support for CXL DVSEC Sean V Kelley
2020-04-15  0:47 ` [PATCH v5 1/2] pciutils: Decode available DVSEC details Sean V Kelley
2020-04-15  0:47 ` [PATCH v5 2/2] pciutils: Decode Compute eXpress Link DVSEC Sean V Kelley
2020-04-18  8:36   ` Jay Fang
2020-04-20 16:21     ` Sean V Kelley
2020-04-20 17:47       ` Bjorn Helgaas
2020-04-20 17:54         ` Sean V Kelley
2020-04-27  3:22         ` Jay Fang

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