From: "Pali Rohár" <pali@kernel.org> To: "Jason Cooper" <jason@lakedaemon.net>, "Andrew Lunn" <andrew@lunn.ch>, "Gregory Clement" <gregory.clement@bootlin.com>, "Sebastian Hesselbarth" <sebastian.hesselbarth@gmail.com>, "Rob Herring" <robh+dt@kernel.org>, "Thomas Petazzoni" <thomas.petazzoni@bootlin.com>, "Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>, "Andrew Murray" <amurray@thegoodpenguin.co.uk>, "Bjorn Helgaas" <bhelgaas@google.com>, "Remi Pommarel" <repk@triplefau.lt>, "Marek Behún" <marek.behun@nic.cz>, "Tomasz Maciej Nowak" <tmn505@gmail.com>, Xogium <contact@xogium.me> Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 1/8] PCI: aardvark: Set controller speed from Device Tree max-link-speed Date: Wed, 15 Apr 2020 18:00:47 +0200 [thread overview] Message-ID: <20200415160054.951-2-pali@kernel.org> (raw) In-Reply-To: <20200415160054.951-1-pali@kernel.org> bindings/pci/pci.txt defines standard DT property max-link-speed for specifying PCI gen of link. Read this property from Device Tree via of_pci_get_max_link_speed() function and use it for configuring aardvark PCI controller gen speed. Before this change aardvark PCI gen speed was configured always to hardcoded value gen2. When Device Tree does not specify max-link-speed property use by default gen3 value, maximum which aardvark PCI controller supports. Signed-off-by: Pali Rohár <pali@kernel.org> --- drivers/pci/controller/pci-aardvark.c | 32 ++++++++++++++++++++++----- 1 file changed, 27 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 2a20b649f40c..ad4f0fa57624 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -253,8 +253,30 @@ static void advk_pcie_wait_for_retrain(struct advk_pcie *pcie) } } +static void advk_pcie_setup_link_speed(struct advk_pcie *pcie, int link_speed) +{ + u32 reg; + + dev_info(&pcie->pdev->dev, "setup link speed to %d\n", link_speed); + + reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); + reg &= ~PCIE_GEN_SEL_MSK; + + if (link_speed == 3) + reg |= SPEED_GEN_3; + else if (link_speed == 2) + reg |= SPEED_GEN_2; + else + reg |= SPEED_GEN_1; + + advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); +} + static void advk_pcie_setup_hw(struct advk_pcie *pcie) { + struct device *dev = &pcie->pdev->dev; + struct device_node *node = dev->of_node; + int max_link_speed; u32 reg; /* Set to Direct mode */ @@ -288,11 +310,11 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) PCIE_CORE_CTRL2_TD_ENABLE; advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); - /* Set GEN2 */ - reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); - reg &= ~PCIE_GEN_SEL_MSK; - reg |= SPEED_GEN_2; - advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); + /* Set max link speed */ + max_link_speed = of_pci_get_max_link_speed(node); + if (max_link_speed <= 0 || max_link_speed > 3) + max_link_speed = 3; + advk_pcie_setup_link_speed(pcie, max_link_speed); /* Set lane X1 */ reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); -- 2.20.1
next prev parent reply other threads:[~2020-04-15 16:01 UTC|newest] Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-04-15 16:00 [PATCH 0/8] PCI: aardvark: Fix support for Turris MOX and Compex wifi cards Pali Rohár 2020-04-15 16:00 ` Pali Rohár [this message] 2020-04-15 16:00 ` [PATCH 2/8] dts: espressobin: Define max-link-speed for pcie0 Pali Rohár 2020-04-19 3:19 ` Marek Behun 2020-04-15 16:00 ` [PATCH 3/8] PCI: aardvark: Start link training immediately after enabling link training Pali Rohár 2020-04-15 16:00 ` [PATCH 4/8] PCI: aardvark: Do not overwrite Link Status register and ASPM Control bits in Link Control register Pali Rohár 2020-04-15 16:03 ` [PATCH 5/8] PCI: aardvark: Set final controller speed based on negotiated link speed Pali Rohár 2020-04-19 3:17 ` Marek Behun 2020-04-15 16:03 ` [PATCH 6/8] PCI: aardvark: Add support for issuing PERST via GPIO Pali Rohár 2020-04-19 3:23 ` Marek Behun 2020-04-15 16:03 ` [PATCH 7/8] dts: aardvark: Route pcie reset pin to gpio function and define reset-gpios for pcie Pali Rohár 2020-04-19 3:54 ` Marek Behun 2020-04-15 16:03 ` [PATCH 8/8] PCI: aardvark: Add FIXME for code which access PCIE_CORE_CMD_STATUS_REG Pali Rohár 2020-04-15 16:18 ` Pali Rohár 2020-04-16 15:50 ` [PATCH 0/8] PCI: aardvark: Fix support for Turris MOX and Compex wifi cards Tomasz Maciej Nowak 2020-04-19 4:01 ` Marek Behun
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