From: "Pali Rohár" <pali@kernel.org> To: "Jason Cooper" <jason@lakedaemon.net>, "Andrew Lunn" <andrew@lunn.ch>, "Gregory Clement" <gregory.clement@bootlin.com>, "Sebastian Hesselbarth" <sebastian.hesselbarth@gmail.com>, "Rob Herring" <robh+dt@kernel.org>, "Thomas Petazzoni" <thomas.petazzoni@bootlin.com>, "Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>, "Andrew Murray" <amurray@thegoodpenguin.co.uk>, "Bjorn Helgaas" <bhelgaas@google.com>, "Remi Pommarel" <repk@triplefau.lt>, "Marek Behún" <marek.behun@nic.cz>, "Tomasz Maciej Nowak" <tmn505@gmail.com>, Xogium <contact@xogium.me> Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 3/8] PCI: aardvark: Start link training immediately after enabling link training Date: Wed, 15 Apr 2020 18:00:49 +0200 [thread overview] Message-ID: <20200415160054.951-4-pali@kernel.org> (raw) In-Reply-To: <20200415160054.951-1-pali@kernel.org> Adding even 100ms (PCI_PM_D3COLD_WAIT) delay between enabling link training and starting link training cause that some Compex WLE900VX cards are not detected. So move code for enabling link training after PCI_PM_D3COLD_WAIT delay. This change fixes Compex WLE900VX cards detection on Turris MOX after cold boot. Fixes: f4c7d053d7f7 ("PCI: aardvark: Wait for endpoint to be ready before training link") Signed-off-by: Pali Rohár <pali@kernel.org> --- drivers/pci/controller/pci-aardvark.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index ad4f0fa57624..756b31c4d20b 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -322,11 +322,6 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) reg |= LANE_COUNT_1; advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); - /* Enable link training */ - reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); - reg |= LINK_TRAINING_EN; - advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); - /* Enable MSI */ reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); reg |= PCIE_CORE_CTRL2_MSI_ENABLE; @@ -368,6 +363,16 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) */ msleep(PCI_PM_D3COLD_WAIT); + /* + * Do "Enable link training" and "Start link training" in a row without + * any delay between them. Adding even 100ms delay (PCI_PM_D3COLD_WAIT) + * cause that some Compex WLE900VX cards are not detected. + */ + + /* Enable link training */ + reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); + reg |= LINK_TRAINING_EN; + advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); /* Start link training */ reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG); reg |= PCIE_CORE_LINK_TRAINING; -- 2.20.1
next prev parent reply other threads:[~2020-04-15 16:02 UTC|newest] Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-04-15 16:00 [PATCH 0/8] PCI: aardvark: Fix support for Turris MOX and Compex wifi cards Pali Rohár 2020-04-15 16:00 ` [PATCH 1/8] PCI: aardvark: Set controller speed from Device Tree max-link-speed Pali Rohár 2020-04-15 16:00 ` [PATCH 2/8] dts: espressobin: Define max-link-speed for pcie0 Pali Rohár 2020-04-19 3:19 ` Marek Behun 2020-04-15 16:00 ` Pali Rohár [this message] 2020-04-15 16:00 ` [PATCH 4/8] PCI: aardvark: Do not overwrite Link Status register and ASPM Control bits in Link Control register Pali Rohár 2020-04-15 16:03 ` [PATCH 5/8] PCI: aardvark: Set final controller speed based on negotiated link speed Pali Rohár 2020-04-19 3:17 ` Marek Behun 2020-04-15 16:03 ` [PATCH 6/8] PCI: aardvark: Add support for issuing PERST via GPIO Pali Rohár 2020-04-19 3:23 ` Marek Behun 2020-04-15 16:03 ` [PATCH 7/8] dts: aardvark: Route pcie reset pin to gpio function and define reset-gpios for pcie Pali Rohár 2020-04-19 3:54 ` Marek Behun 2020-04-15 16:03 ` [PATCH 8/8] PCI: aardvark: Add FIXME for code which access PCIE_CORE_CMD_STATUS_REG Pali Rohár 2020-04-15 16:18 ` Pali Rohár 2020-04-16 15:50 ` [PATCH 0/8] PCI: aardvark: Fix support for Turris MOX and Compex wifi cards Tomasz Maciej Nowak 2020-04-19 4:01 ` Marek Behun
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