From: <chuanjia.liu@mediatek.com>
To: <robh+dt@kernel.org>, <bhelgaas@google.com>,
<matthias.bgg@gmail.com>, <lorenzo.pieralisi@arm.com>,
<amurray@thegoodpenguin.co.uk>
Cc: <linux-pci@vger.kernel.org>, <linux-mediatek@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <ryder.lee@mediatek.com>,
<chuanjia.liu@mediatek.com>, <jianjun.wang@mediatek.com>,
<srv_heupstream@mediatek.com>
Subject: [PATCH 0/4] Spilt PCIe node to comply with hardware design
Date: Fri, 17 Apr 2020 17:35:01 +0800 [thread overview]
Message-ID: <20200417093505.13978-1-chuanjia.liu@mediatek.com> (raw)
There are two independent PCIe controllers in MT2712/MT7622 platform,
and each of them should contain an independent MSI domain.
In current architecture, MSI domain will be inherited from the root
bridge, and all of the devices will share the same MSI domain.
Hence that, the PCIe devices will not work properly if the irq number
which required is more than 32.
Split the PCIe node for MT2712/MT7622 platform to fix MSI issue and
comply with the hardware design.
chuanjia.liu (4):
dt-bindings: PCI: Mediatek: Update PCIe binding
PCI: mediatek: Use regmap to get shared pcie-cfg base
arm64: dts: mediatek: Split PCIe node for MT2712/MT7622
ARM: dts: mediatek: Update mt7629 PCIe node
.../bindings/pci/mediatek-pcie-cfg.yaml | 38 ++++++
.../devicetree/bindings/pci/mediatek-pcie.txt | 120 ++++++++++++------
arch/arm/boot/dts/mt7629-rfb.dts | 3 +-
arch/arm/boot/dts/mt7629.dtsi | 23 ++--
arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 51 +++++---
.../dts/mediatek/mt7622-bananapi-bpi-r64.dts | 16 +--
arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 6 +-
arch/arm64/boot/dts/mediatek/mt7622.dtsi | 68 ++++++----
drivers/pci/controller/pcie-mediatek.c | 25 +++-
9 files changed, 234 insertions(+), 116 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml
--
2.18.0
reply other threads:[~2020-04-17 9:39 UTC|newest]
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