From: Kishon Vijay Abraham I <kishon@ti.com>
To: Tom Joseph <tjoseph@cadence.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Rob Herring <robh+dt@kernel.org>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Andrew Murray <amurray@thegoodpenguin.co.uk>
Cc: Arnd Bergmann <arnd@arndb.de>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>
Subject: [PATCH v3 00/14] Add PCIe support to TI's J721E SoC
Date: Fri, 17 Apr 2020 18:27:39 +0530 [thread overview]
Message-ID: <20200417125753.13021-1-kishon@ti.com> (raw)
TI's J721E SoC uses Cadence PCIe core to implement both RC mode
and EP mode.
The high level features are:
*) Supports Legacy, MSI and MSI-X interrupt
*) Supports upto GEN4 speed mode
*) Supports SR-IOV
*) Supports multiple physical function
*) Ability to route all transactions via SMMU
This patch series
*) Add support in Cadence PCIe core to be used for TI's J721E SoC
*) Add a driver for J721E PCIe wrapper
v1 of the series can be found @ [1]
v2 of the series can be found @ [2]
Changes from v2:
1) Converting Cadence binding to YAML schema was done as a
separate series [3] & [4]. [3] is merged and [4] is
pending.
2) Included MSI-X support in this series
3) Added link down interrupt handling (only error message)
4) Rebased to latest 5.7-rc1
5) Adapted TI J721E binding to [3] & [4]
Changes from v1:
1) Added DT schemas cdns-pcie-host.yaml, cdns-pcie-ep.yaml and
cdns-pcie.yaml for Cadence PCIe core and included it in
TI's PCIe DT schema.
2) Added cpu_addr_fixup() for Cadence Platform driver.
3) Fixed subject/description/renamed functions as commented by
Andrew Murray.
[1] -> http://lore.kernel.org/r/20191209092147.22901-1-kishon@ti.com
[2] -> http://lore.kernel.org/r/20200106102058.19183-1-kishon@ti.com
[3] -> http://lore.kernel.org/r/20200305103017.16706-1-kishon@ti.com
[4] -> http://lore.kernel.org/r/20200417114322.31111-1-kishon@ti.com
Alan Douglas (1):
PCI: cadence: Add MSI-X support to Endpoint driver
Kishon Vijay Abraham I (13):
PCI: cadence: Fix cdns_pcie_{host|ep}_setup() error path
linux/kernel.h: Add PTR_ALIGN_DOWN macro
PCI: cadence: Add support to use custom read and write accessors
PCI: cadence: Add support to start link and verify link status
PCI: cadence: Add read/write accessors to perform only 32-bit accesses
PCI: cadence: Allow pci_host_bridge to have custom pci_ops
PCI: cadence: Add new *ops* for CPU addr fixup
PCI: cadence: Fix updating Vendor ID and Subsystem Vendor ID register
dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC
dt-bindings: PCI: Add EP mode dt-bindings for TI's J721E SoC
PCI: j721e: Add TI J721E PCIe driver
misc: pci_endpoint_test: Add J721E in pci_device_id table
MAINTAINERS: Add Kishon Vijay Abraham I for TI J721E SoC PCIe
.../bindings/pci/ti,j721e-pci-ep.yaml | 89 ++++
.../bindings/pci/ti,j721e-pci-host.yaml | 113 ++++
MAINTAINERS | 4 +-
drivers/misc/pci_endpoint_test.c | 9 +
drivers/pci/controller/cadence/Kconfig | 23 +
drivers/pci/controller/cadence/Makefile | 1 +
drivers/pci/controller/cadence/pci-j721e.c | 500 ++++++++++++++++++
.../pci/controller/cadence/pcie-cadence-ep.c | 129 ++++-
.../controller/cadence/pcie-cadence-host.c | 59 ++-
.../controller/cadence/pcie-cadence-plat.c | 13 +
drivers/pci/controller/cadence/pcie-cadence.c | 48 +-
drivers/pci/controller/cadence/pcie-cadence.h | 158 +++++-
include/linux/kernel.h | 1 +
13 files changed, 1105 insertions(+), 42 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
create mode 100644 Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
create mode 100644 drivers/pci/controller/cadence/pci-j721e.c
--
2.17.1
next reply other threads:[~2020-04-17 12:58 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-17 12:57 Kishon Vijay Abraham I [this message]
2020-04-17 12:57 ` [PATCH v3 01/14] PCI: cadence: Fix cdns_pcie_{host|ep}_setup() error path Kishon Vijay Abraham I
2020-04-17 12:57 ` [PATCH v3 02/14] linux/kernel.h: Add PTR_ALIGN_DOWN macro Kishon Vijay Abraham I
2020-04-17 12:57 ` [PATCH v3 03/14] PCI: cadence: Add support to use custom read and write accessors Kishon Vijay Abraham I
2020-04-17 12:57 ` [PATCH v3 04/14] PCI: cadence: Add support to start link and verify link status Kishon Vijay Abraham I
2020-04-17 12:57 ` [PATCH v3 05/14] PCI: cadence: Add read/write accessors to perform only 32-bit accesses Kishon Vijay Abraham I
2020-04-17 12:57 ` [PATCH v3 06/14] PCI: cadence: Allow pci_host_bridge to have custom pci_ops Kishon Vijay Abraham I
2020-04-17 12:57 ` [PATCH v3 07/14] PCI: cadence: Add new *ops* for CPU addr fixup Kishon Vijay Abraham I
2020-04-17 12:57 ` [PATCH v3 08/14] PCI: cadence: Fix updating Vendor ID and Subsystem Vendor ID register Kishon Vijay Abraham I
2020-04-17 12:57 ` [PATCH v3 09/14] PCI: cadence: Add MSI-X support to Endpoint driver Kishon Vijay Abraham I
2020-04-30 1:55 ` Rob Herring
2020-05-06 3:58 ` Kishon Vijay Abraham I
2020-04-17 12:57 ` [PATCH v3 10/14] dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC Kishon Vijay Abraham I
2020-04-30 2:11 ` Rob Herring
2020-04-17 12:57 ` [PATCH v3 11/14] dt-bindings: PCI: Add EP " Kishon Vijay Abraham I
2020-04-30 2:13 ` Rob Herring
2020-04-17 12:57 ` [PATCH v3 12/14] PCI: j721e: Add TI J721E PCIe driver Kishon Vijay Abraham I
2020-04-30 2:11 ` Rob Herring
2020-05-06 4:18 ` Kishon Vijay Abraham I
2020-04-17 12:57 ` [PATCH v3 13/14] misc: pci_endpoint_test: Add J721E in pci_device_id table Kishon Vijay Abraham I
2020-04-17 12:57 ` [PATCH v3 14/14] MAINTAINERS: Add Kishon Vijay Abraham I for TI J721E SoC PCIe Kishon Vijay Abraham I
2020-04-17 15:19 ` Joe Perches
2020-05-06 3:54 ` Kishon Vijay Abraham I
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