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From: Sean V Kelley <sean.v.kelley@linux.intel.com>
To: mj@ucw.cz, bhelgaas@google.com
Cc: linux-pci@vger.kernel.org, Sean V Kelley <sean.v.kelley@linux.intel.com>
Subject: [PATCH v6 0/2] pciutils: Add basic decode support for CXL DVSEC
Date: Mon, 20 Apr 2020 15:14:42 -0700	[thread overview]
Message-ID: <20200420221444.2641935-1-sean.v.kelley@linux.intel.com> (raw)

Changes since v5 [1]:

- There can be multiple vendor specific DVSEC IDs associated with CXL.
(Bjorn Helgaas)

[1] https://lore.kernel.org/linux-pci/20200415004751.2103963-1-sean.v.kelley@linux.intel.com/

This patch series adds support for basic lspci decode of Compute eXpress Link[2],
a new CPU interconnect building upon PCIe. As a foundation for the CXL
support it adds separate Designated Vendor-Specific Capability (DVSEC) defines
and a cap function so as to align with PCIe r5.0, sec 7.9.6.2 terms and
provide available details. It makes use of the DVSEC Vendor ID and DVSEC ID so as
to identify a CXL capable device.

[2] https://www.computeexpresslink.org/

Sean V Kelley (2):
  pciutils: Decode available DVSEC details
  pciutils: Decode Compute eXpress Link DVSEC

 lib/header.h        |  24 ++++
 ls-ecaps.c          |  79 +++++++++-
 tests/cap-dvsec     | 340 ++++++++++++++++++++++++++++++++++++++++++++
 tests/cap-dvsec-cxl | 340 ++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 782 insertions(+), 1 deletion(-)
 create mode 100644 tests/cap-dvsec
 create mode 100644 tests/cap-dvsec-cxl

--
2.26.0


             reply	other threads:[~2020-04-20 22:14 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-20 22:14 Sean V Kelley [this message]
2020-04-20 22:14 ` [PATCH v6 1/2] pciutils: Decode available DVSEC details Sean V Kelley
2020-04-20 22:14 ` [PATCH v6 2/2] pciutils: Decode Compute eXpress Link DVSEC Sean V Kelley
2020-05-04 16:20 ` [PATCH v6 0/2] pciutils: Add basic decode support for CXL DVSEC Sean V Kelley

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