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From: Bjorn Helgaas <helgaas@kernel.org>
To: "Marek Behún" <marek.behun@nic.cz>
Cc: linux-pci@vger.kernel.org, "Jason Cooper" <jason@lakedaemon.net>,
	"Andrew Lunn" <andrew@lunn.ch>,
	"Gregory Clement" <gregory.clement@bootlin.com>,
	"Sebastian Hesselbarth" <sebastian.hesselbarth@gmail.com>,
	"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
	"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
	"Andrew Murray" <amurray@thegoodpenguin.co.uk>,
	"Remi Pommarel" <repk@triplefau.lt>,
	"Tomasz Maciej Nowak" <tmn505@gmail.com>,
	Xogium <contact@xogium.me>, "Pali Rohár" <pali@kernel.org>,
	"Rob Herring" <robh@kernel.org>
Subject: Re: [PATCH v2 2/9] PCI: aardvark: don't write to read-only register
Date: Thu, 23 Apr 2020 12:27:13 -0500	[thread overview]
Message-ID: <20200423172713.GA191930@google.com> (raw)
In-Reply-To: <20200421111701.17088-3-marek.behun@nic.cz>

[+cc Rob]

In the next round, please capitalize the first word of the subjects of
the whole series to match:

  $ git log --oneline drivers/pci/controller/pci-aardvark.c
  4e5be6f81be7 ("PCI: aardvark: Use pci_parse_request_of_pci_ranges()")
  e078723f9ccc ("PCI: aardvark: Fix big endian support")
  7fbcb5da811b ("PCI: aardvark: Don't rely on jiffies while holding spinlock")
  c0f05a6ab525 ("PCI: aardvark: Fix PCI_EXP_RTCTL register configuration")
  f4c7d053d7f7 ("PCI: aardvark: Wait for endpoint to be ready before training link")
  364b3f1ff8f0 ("PCI: aardvark: Use LTSSM state to build link training flag")

The important thing for the subject of this patch is not the "don't
write to read-only register" part; it's true that there's no point in
writing to read-only registers, but removing that write would not fix
any bugs.

The important thing is that we shouldn't blindly enable ASPM L0s, so
that's what the subject should mention.

On Tue, Apr 21, 2020 at 01:16:54PM +0200, Marek Behún wrote:
> From: Pali Rohár <pali@kernel.org>
> 
> Trying to change Link Status register does not have any effect as this
> is a read-only register. Trying to overwrite bits for Negotiated Link
> Width does not make sense.
> 
> In future proper change of link width can be done via Lane Count Select
> bits in PCIe Control 0 register.
> 
> Trying to unconditionally enable ASPM L0s via ASPM Control bits in Link
> Control register is wrong. There should be at least some detection if
> endpoint supports L0s as isn't mandatory.
> 
> Moreover ASPM Control bits in Link Control register are controlled by
> pcie/aspm.c code which sets it according to system ASPM settings,
> immediately after aardvark driver probes. So setting these bits by
> aardvark driver has no long running effect.
> 
> Remove code which touches ASPM L0s bits from this driver and let
> kernel's ASPM implementation to set ASPM state properly.
> 
> Some users are reporting issues that this code is problematic for some
> Intel wifi cards and removing it fixes them, see e.g.:
> https://bugzilla.kernel.org/show_bug.cgi?id=196339
> 
> If problems with Intel wifi cards occur even after this commit, then
> pcie/aspm.c code could be modified / hooked to not enable ASPM L0s state
> for affected problematic cards.
> 
> Signed-off-by: Pali Rohár <pali@kernel.org>
> ---
>  drivers/pci/controller/pci-aardvark.c | 4 ----
>  1 file changed, 4 deletions(-)
> 
> diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
> index b59198a102d0..551d98174613 100644
> --- a/drivers/pci/controller/pci-aardvark.c
> +++ b/drivers/pci/controller/pci-aardvark.c
> @@ -356,10 +356,6 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
>  
>  	advk_pcie_wait_for_link(pcie);
>  
> -	reg = PCIE_CORE_LINK_L0S_ENTRY |
> -		(1 << PCIE_CORE_LINK_WIDTH_SHIFT);
> -	advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
> -
>  	reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
>  	reg |= PCIE_CORE_CMD_MEM_ACCESS_EN |
>  		PCIE_CORE_CMD_IO_ACCESS_EN |
> -- 
> 2.24.1
> 

  reply	other threads:[~2020-04-23 17:27 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-21 11:16 [PATCH v2 0/9] PCI: aardvark: Fix support for Turris MOX and Compex wifi cards Marek Behún
2020-04-21 11:16 ` [PATCH v2 1/9] PCI: aardvark: train link immediately after enabling training Marek Behún
2020-04-21 11:16 ` [PATCH v2 2/9] PCI: aardvark: don't write to read-only register Marek Behún
2020-04-23 17:27   ` Bjorn Helgaas [this message]
2020-04-23 17:51     ` Pali Rohár
2020-04-21 11:16 ` [PATCH v2 3/9] PCI: aardvark: improve link training Marek Behún
2020-04-23 18:39   ` Bjorn Helgaas
2020-04-23 18:56     ` Pali Rohár
2020-04-24 12:49       ` Pali Rohár
2020-04-21 11:16 ` [PATCH v2 4/9] PCI: aardvark: issue PERST via GPIO Marek Behún
2020-04-23 18:41   ` Bjorn Helgaas
2020-04-23 19:02     ` Pali Rohár
2020-04-23 22:17       ` Bjorn Helgaas
2020-04-23 22:23         ` Pali Rohár
2020-04-23 22:40           ` Bjorn Helgaas
2020-04-24  8:13             ` Pali Rohár
2020-04-24  9:25   ` Pali Rohár
2020-04-21 11:16 ` [PATCH v2 5/9] PCI: aardvark: add FIXME comment for PCIE_CORE_CMD_STATUS_REG access Marek Behún
2020-04-23 18:44   ` Bjorn Helgaas
2020-04-23 19:06     ` Pali Rohár
2020-04-21 11:16 ` [PATCH v2 6/9] PCI: aardvark: add PHY support Marek Behún
2020-04-21 11:16 ` [PATCH v2 7/9] dt-bindings: PCI: aardvark: describe new properties Marek Behún
2020-05-11 18:24   ` Rob Herring
2020-04-21 11:17 ` [PATCH v2 8/9] arm64: dts: marvell: armada-37xx: set pcie_reset_pin to gpio function Marek Behún
2020-04-21 11:17 ` [PATCH v2 9/9] arm64: dts: marvell: armada-37xx: move PCIe comphy handle property Marek Behún
2020-04-21 11:42 ` [PATCH v2 0/9] PCI: aardvark: Fix support for Turris MOX and Compex wifi cards Pali Rohár

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