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* [PATCH v6 0/5] Loongson PCI Generic Driver
@ 2020-04-27  6:05 Jiaxun Yang
  2020-04-27  6:05 ` [PATCH v6 1/5] PCI: Don't disable decoding when mmio_always_on is set Jiaxun Yang
                   ` (9 more replies)
  0 siblings, 10 replies; 63+ messages in thread
From: Jiaxun Yang @ 2020-04-27  6:05 UTC (permalink / raw)
  To: linux-mips
  Cc: Jiaxun Yang, Bjorn Helgaas, Rob Herring, Thomas Bogendoerfer,
	Huacai Chen, Lorenzo Pieralisi, Paul Burton, linux-pci,
	devicetree, linux-kernel

Hi,

This series converts Loongson PCI into a generic PCI controller
driver and adds support for LS2K SoC and LS7A PCH's PCI support.

Is it possible to let patch 1~3 go through PCI tree and patch
4~5 go through MIPS tree?

Thanks.

v6: Drop first the patch of previous versions. Driver code clean-ups
according to rob's suggestion.

It looks like I had a wrong impression on generic IO port handeling
and now the issue has been fixed, I implemented PCI_IOBASE for MIPS[1].
Now the address is uniform here.

[1]: https://patchwork.kernel.org/cover/11510499/

Jiaxun Yang (5):
  PCI: Don't disable decoding when mmio_always_on is set
  PCI: Add Loongson PCI Controller support
  dt-bindings: Document Loongson PCI Host Controller
  MIPS: DTS: Loongson64: Add PCI Controller Node
  MIPS: Loongson64: Switch to generic PCI driver

 .../devicetree/bindings/pci/loongson.yaml     |  62 +++++
 arch/mips/Kconfig                             |   1 +
 arch/mips/boot/dts/loongson/rs780e-pch.dtsi   |  12 +
 arch/mips/loongson64/Makefile                 |   2 +-
 arch/mips/loongson64/vbios_quirk.c            |  29 ++
 arch/mips/pci/Makefile                        |   1 -
 arch/mips/pci/fixup-loongson3.c               |  71 -----
 arch/mips/pci/ops-loongson3.c                 | 116 --------
 drivers/pci/controller/Kconfig                |  10 +
 drivers/pci/controller/Makefile               |   1 +
 drivers/pci/controller/pci-loongson.c         | 251 ++++++++++++++++++
 drivers/pci/probe.c                           |   2 +-
 12 files changed, 368 insertions(+), 190 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pci/loongson.yaml
 create mode 100644 arch/mips/loongson64/vbios_quirk.c
 delete mode 100644 arch/mips/pci/fixup-loongson3.c
 delete mode 100644 arch/mips/pci/ops-loongson3.c
 create mode 100644 drivers/pci/controller/pci-loongson.c

-- 
2.26.0.rc2


^ permalink raw reply	[flat|nested] 63+ messages in thread

* [PATCH v6 1/5] PCI: Don't disable decoding when mmio_always_on is set
  2020-04-27  6:05 [PATCH v6 0/5] Loongson PCI Generic Driver Jiaxun Yang
@ 2020-04-27  6:05 ` Jiaxun Yang
  2020-04-27  7:42   ` Philippe Mathieu-Daudé
  2020-04-27  6:05 ` [PATCH v6 2/5] PCI: Add Loongson PCI Controller support Jiaxun Yang
                   ` (8 subsequent siblings)
  9 siblings, 1 reply; 63+ messages in thread
From: Jiaxun Yang @ 2020-04-27  6:05 UTC (permalink / raw)
  To: linux-mips
  Cc: Jiaxun Yang, Bjorn Helgaas, Rob Herring, Thomas Bogendoerfer,
	Huacai Chen, Lorenzo Pieralisi, Paul Burton, linux-pci,
	devicetree, linux-kernel

Don't disable MEM/IO decoing when a device have both non_compliant_bars
and mmio_always_on.

That would allow us quirk devices with junk in BARs but can't disable
their decoding.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 drivers/pci/probe.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 77b8a145c39b..d9c2c3301a8a 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -1822,7 +1822,7 @@ int pci_setup_device(struct pci_dev *dev)
 	/* Device class may be changed after fixup */
 	class = dev->class >> 8;
 
-	if (dev->non_compliant_bars) {
+	if (dev->non_compliant_bars && !dev->mmio_always_on) {
 		pci_read_config_word(dev, PCI_COMMAND, &cmd);
 		if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
 			pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
-- 
2.26.0.rc2


^ permalink raw reply related	[flat|nested] 63+ messages in thread

* [PATCH v6 2/5] PCI: Add Loongson PCI Controller support
  2020-04-27  6:05 [PATCH v6 0/5] Loongson PCI Generic Driver Jiaxun Yang
  2020-04-27  6:05 ` [PATCH v6 1/5] PCI: Don't disable decoding when mmio_always_on is set Jiaxun Yang
@ 2020-04-27  6:05 ` Jiaxun Yang
  2020-04-27  6:29   ` Huacai Chen
  2020-04-27  6:05 ` [PATCH v6 3/5] dt-bindings: Document Loongson PCI Host Controller Jiaxun Yang
                   ` (7 subsequent siblings)
  9 siblings, 1 reply; 63+ messages in thread
From: Jiaxun Yang @ 2020-04-27  6:05 UTC (permalink / raw)
  To: linux-mips
  Cc: Jiaxun Yang, Bjorn Helgaas, Rob Herring, Thomas Bogendoerfer,
	Huacai Chen, Lorenzo Pieralisi, Paul Burton, linux-pci,
	devicetree, linux-kernel

This controller can be found on Loongson-2K SoC, Loongson-3
systems with RS780E/LS7A PCH.

The RS780E part of code was previously located at
arch/mips/pci/ops-loongson3.c and now it can use generic PCI
driver implementation.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>

--
v2:
	- Clean up according to rob's suggestions
	- Claim that it can't work as a module
v3:
	- Fix a typo
v4:
	- More clean-ups: Drop flag check, use devfn
---
 drivers/pci/controller/Kconfig        |  10 +
 drivers/pci/controller/Makefile       |   1 +
 drivers/pci/controller/pci-loongson.c | 251 ++++++++++++++++++++++++++
 3 files changed, 262 insertions(+)
 create mode 100644 drivers/pci/controller/pci-loongson.c

diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 91bfdb784829..ae36edb1d7db 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -258,6 +258,16 @@ config PCI_HYPERV_INTERFACE
 	  The Hyper-V PCI Interface is a helper driver allows other drivers to
 	  have a common interface with the Hyper-V PCI frontend driver.
 
+config PCI_LOONGSON
+	bool "LOONGSON PCI Controller"
+	depends on MACH_LOONGSON64 || COMPILE_TEST
+	depends on OF
+	depends on PCI_QUIRKS
+	default MACH_LOONGSON64
+	help
+	  Say Y here if you want to enable PCI controller support on
+	  Loongson systems.
+
 source "drivers/pci/controller/dwc/Kconfig"
 source "drivers/pci/controller/mobiveil/Kconfig"
 source "drivers/pci/controller/cadence/Kconfig"
diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
index 158c59771824..fbac4b0190a0 100644
--- a/drivers/pci/controller/Makefile
+++ b/drivers/pci/controller/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
 obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
 obj-$(CONFIG_VMD) += vmd.o
 obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
+obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o
 # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
 obj-y				+= dwc/
 obj-y				+= mobiveil/
diff --git a/drivers/pci/controller/pci-loongson.c b/drivers/pci/controller/pci-loongson.c
new file mode 100644
index 000000000000..6cb8de384d36
--- /dev/null
+++ b/drivers/pci/controller/pci-loongson.c
@@ -0,0 +1,251 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Loongson PCI Host Controller Driver
+ *
+ * Copyright (C) 2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
+ */
+
+#include <linux/of_device.h>
+#include <linux/of_pci.h>
+#include <linux/pci.h>
+#include <linux/pci_ids.h>
+
+#include "../pci.h"
+
+/* Device IDs */
+#define DEV_PCIE_PORT_0	0x7a09
+#define DEV_PCIE_PORT_1	0x7a19
+#define DEV_PCIE_PORT_2	0x7a29
+
+#define DEV_LS2K_APB	0x7a02
+#define DEV_LS7A_CONF	0x7a10
+#define DEV_LS7A_LPC	0x7a0c
+
+#define FLAG_CFG0	BIT(0)
+#define FLAG_CFG1	BIT(1)
+#define FLAG_DEV_FIX	BIT(2)
+
+struct loongson_pci {
+	void __iomem *cfg0_base;
+	void __iomem *cfg1_base;
+	struct platform_device *pdev;
+	u32 flags;
+};
+
+/* Fixup wrong class code in PCIe bridges */
+static void bridge_class_quirk(struct pci_dev *dev)
+{
+	dev->class = PCI_CLASS_BRIDGE_PCI << 8;
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON,
+			DEV_PCIE_PORT_0, bridge_class_quirk);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON,
+			DEV_PCIE_PORT_1, bridge_class_quirk);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON,
+			DEV_PCIE_PORT_2, bridge_class_quirk);
+
+static void system_bus_quirk(struct pci_dev *pdev)
+{
+	u16 tmp;
+
+	pdev->mmio_always_on = 1;
+	pdev->non_compliant_bars = 1;
+	/* Enable MEM & IO Decoding */
+	pci_read_config_word(pdev, PCI_STATUS, &tmp);
+	tmp |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
+	pci_write_config_word(pdev, PCI_STATUS, tmp);
+}
+
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
+			DEV_LS2K_APB, system_bus_quirk);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
+			DEV_LS7A_CONF, system_bus_quirk);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
+			DEV_LS7A_LPC, system_bus_quirk);
+
+static void loongson_mrrs_quirk(struct pci_dev *dev)
+{
+	struct pci_bus *bus = dev->bus;
+	struct pci_dev *bridge;
+	static const struct pci_device_id bridge_devids[] = {
+		{ PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_0) },
+		{ PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_1) },
+		{ PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_2) },
+		{ 0, },
+	};
+
+
+	/* look for the matching bridge */
+	while (!pci_is_root_bus(bus)) {
+		bridge = bus->self;
+		bus = bus->parent;
+		/*
+		 * Some Loongson PCIE ports has a h/w limitation of
+		 * 256 bytes maximum read request size. It can't handle
+		 * anything higher than this. So force this limit on
+		 * any devices attached under these ports.
+		 */
+		if (pci_match_id(bridge_devids, bridge)) {
+			if (pcie_get_readrq(dev) > 256) {
+				dev_info(&dev->dev, "limiting MRRS to 256\n");
+				pcie_set_readrq(dev, 256);
+			}
+			break;
+		}
+	}
+}
+DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, loongson_mrrs_quirk);
+
+static void __iomem *cfg1_map(struct loongson_pci *priv, int bus,
+				unsigned int devfn, int where)
+{
+	unsigned long addroff = 0x0;
+
+	if (bus != 0)
+		addroff |= BIT(28); /* Type 1 Access */
+	addroff |= (where & 0xff) | ((where & 0xf00) << 16);
+	addroff |= (bus << 16) | (devfn << 8);
+	return priv->cfg1_base + addroff;
+}
+
+static void __iomem *cfg0_map(struct loongson_pci *priv, int bus,
+				unsigned int devfn, int where)
+{
+	unsigned long addroff = 0x0;
+
+	if (bus != 0)
+		addroff |= BIT(24); /* Type 1 Access */
+	addroff |= (bus << 16) | (devfn << 8) | where;
+	return priv->cfg0_base + addroff;
+}
+
+void __iomem *pci_loongson_map_bus(struct pci_bus *bus, unsigned int devfn,
+			       int where)
+{
+	unsigned char busnum = bus->number;
+	struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
+	struct loongson_pci *priv =  pci_host_bridge_priv(bridge);
+
+	/*
+	 * Do not read more than one device on the bus other than
+	 * the host bridge.
+	 */
+	if (bus->primary != 0 && PCI_SLOT(devfn) > 0 &&
+		priv->flags & FLAG_DEV_FIX)
+		return NULL;
+
+	/* CFG0 can only access standard space */
+	if (where < PCI_CFG_SPACE_SIZE && priv->cfg0_base)
+		return cfg0_map(priv, busnum, devfn, where);
+
+	/* CFG1 can access extended space */
+	if (where < PCI_CFG_SPACE_EXP_SIZE && priv->cfg1_base)
+		return cfg1_map(priv, busnum, devfn, where);
+
+	return NULL;
+}
+
+static int loongson_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+	int irq;
+	u8 val;
+
+	irq = of_irq_parse_and_map_pci(dev, slot, pin);
+	if (irq > 0)
+		return irq;
+
+	/* Care i8259 legacy systems */
+	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &val);
+	/* i8259 only have 15 IRQs */
+	if (val > 15)
+		return 0;
+
+	return val;
+}
+
+/* H/w only accept 32-bit PCI operations */
+static struct pci_ops loongson_pci_ops = {
+	.map_bus = pci_loongson_map_bus,
+	.read	= pci_generic_config_read32,
+	.write	= pci_generic_config_write32,
+};
+
+static const struct of_device_id loongson_pci_of_match[] = {
+	{ .compatible = "loongson,rs780e-pci",
+		.data = (void *)(FLAG_CFG0), },
+	{ .compatible = "loongson,ls2k-pci",
+		.data = (void *)(FLAG_CFG0 | FLAG_CFG1 | FLAG_DEV_FIX), },
+	{ .compatible = "loongson,ls7a-pci",
+		.data = (void *)(FLAG_CFG0 | FLAG_CFG1 | FLAG_DEV_FIX), },
+	{}
+};
+
+static int loongson_pci_probe(struct platform_device *pdev)
+{
+	struct loongson_pci *priv;
+	struct device *dev = &pdev->dev;
+	struct device_node *node = dev->of_node;
+	struct pci_host_bridge *bridge;
+	struct resource *regs;
+	int err;
+
+	if (!node)
+		return -ENODEV;
+
+	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*priv));
+	if (!bridge)
+		return -ENODEV;
+
+	priv = pci_host_bridge_priv(bridge);
+	priv->pdev = pdev;
+	priv->flags = (unsigned long)of_device_get_match_data(dev);
+
+	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!regs) {
+		dev_err(dev, "missing mem resources for cfg0\n");
+		return -EINVAL;
+	}
+
+	priv->cfg0_base = devm_pci_remap_cfg_resource(dev, regs);
+	if (IS_ERR(priv->cfg0_base))
+		return PTR_ERR(priv->cfg0_base);
+
+	/* CFG1 is optional */
+	if (priv->flags & FLAG_CFG1) {
+		regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+		if (!regs)
+			dev_info(dev, "missing mem resource for cfg1\n");
+		else {
+			priv->cfg1_base = devm_pci_remap_cfg_resource(dev, regs);
+			if (IS_ERR(priv->cfg1_base))
+				priv->cfg1_base = NULL;
+		}
+	}
+
+	err = pci_parse_request_of_pci_ranges(dev, &bridge->windows,
+						&bridge->dma_ranges, NULL);
+	if (err) {
+		dev_err(dev, "Failed to get bridge resources\n");
+		return err;
+	}
+
+	bridge->dev.parent = dev;
+	bridge->sysdata = priv;
+	bridge->ops = &loongson_pci_ops;
+	bridge->map_irq = loongson_map_irq;
+
+	err = pci_host_probe(bridge);
+	if (err)
+		return err;
+
+	return 0;
+}
+
+static struct platform_driver loongson_pci_driver = {
+	.driver = {
+		.name = "loongson-pci",
+		.of_match_table = loongson_pci_of_match,
+	},
+	.probe = loongson_pci_probe,
+};
+builtin_platform_driver(loongson_pci_driver);
-- 
2.26.0.rc2


^ permalink raw reply related	[flat|nested] 63+ messages in thread

* [PATCH v6 3/5] dt-bindings: Document Loongson PCI Host Controller
  2020-04-27  6:05 [PATCH v6 0/5] Loongson PCI Generic Driver Jiaxun Yang
  2020-04-27  6:05 ` [PATCH v6 1/5] PCI: Don't disable decoding when mmio_always_on is set Jiaxun Yang
  2020-04-27  6:05 ` [PATCH v6 2/5] PCI: Add Loongson PCI Controller support Jiaxun Yang
@ 2020-04-27  6:05 ` Jiaxun Yang
  2020-04-27  6:05 ` [PATCH v6 4/5] MIPS: DTS: Loongson64: Add PCI Controller Node Jiaxun Yang
                   ` (6 subsequent siblings)
  9 siblings, 0 replies; 63+ messages in thread
From: Jiaxun Yang @ 2020-04-27  6:05 UTC (permalink / raw)
  To: linux-mips
  Cc: Jiaxun Yang, Rob Herring, Bjorn Helgaas, Rob Herring,
	Thomas Bogendoerfer, Huacai Chen, Lorenzo Pieralisi, Paul Burton,
	linux-pci, devicetree, linux-kernel

PCI host controller found on Loongson PCHs and SoCs.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../devicetree/bindings/pci/loongson.yaml     | 62 +++++++++++++++++++
 1 file changed, 62 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/loongson.yaml

diff --git a/Documentation/devicetree/bindings/pci/loongson.yaml b/Documentation/devicetree/bindings/pci/loongson.yaml
new file mode 100644
index 000000000000..78c5e32b2faa
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/loongson.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/loongson.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Loongson PCI Host Controller
+
+maintainers:
+  - Jiaxun Yang <jiaxun.yang@flygoat.com>
+
+description: |+
+  PCI host controller found on Loongson PCHs and SoCs.
+
+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+  compatible:
+    oneOf:
+      - const: loongson,rs780e-pci
+      - const: loongson,ls2k-pci
+      - const: loongson,ls7a-pci
+
+  reg:
+    minItems: 1
+    maxItems: 2
+    items:
+      - description: CFG0 standard config space register
+      - description: CFG1 extended config space register
+
+  ranges:
+    minItems: 1
+    maxItems: 3
+
+
+required:
+  - compatible
+  - reg
+  - ranges
+
+examples:
+  - |
+
+    bus {
+        #address-cells = <2>;
+        #size-cells = <2>;
+        pcie@1a000000 {
+            compatible = "loongson,rs780e-pci";
+            device_type = "pci";
+            #address-cells = <3>;
+            #size-cells = <2>;
+
+            // CPU_PHYSICAL(2)  SIZE(2)
+            reg = <0x0 0x1a000000  0x0 0x2000000>;
+
+            // BUS_ADDRESS(3)  CPU_PHYSICAL(2)  SIZE(2)
+            ranges = <0x01000000 0x0 0x00004000  0x0 0x00004000  0x0 0x00004000>,
+                     <0x02000000 0x0 0x40000000  0x0 0x40000000  0x0 0x40000000>;
+        };
+    };
+...
-- 
2.26.0.rc2


^ permalink raw reply related	[flat|nested] 63+ messages in thread

* [PATCH v6 4/5] MIPS: DTS: Loongson64: Add PCI Controller Node
  2020-04-27  6:05 [PATCH v6 0/5] Loongson PCI Generic Driver Jiaxun Yang
                   ` (2 preceding siblings ...)
  2020-04-27  6:05 ` [PATCH v6 3/5] dt-bindings: Document Loongson PCI Host Controller Jiaxun Yang
@ 2020-04-27  6:05 ` Jiaxun Yang
  2020-04-27  6:05 ` [PATCH v6 5/5] MIPS: Loongson64: Switch to generic PCI driver Jiaxun Yang
                   ` (5 subsequent siblings)
  9 siblings, 0 replies; 63+ messages in thread
From: Jiaxun Yang @ 2020-04-27  6:05 UTC (permalink / raw)
  To: linux-mips
  Cc: Jiaxun Yang, Bjorn Helgaas, Rob Herring, Thomas Bogendoerfer,
	Huacai Chen, Lorenzo Pieralisi, Paul Burton, linux-pci,
	devicetree, linux-kernel

Add PCI Host controller node for Loongson64 with RS780E PCH dts.
Note that PCI interrupts are probed via legacy way, as different
machine have different interrupt arrangement, we can't cover all
of them in dt.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 arch/mips/boot/dts/loongson/rs780e-pch.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/mips/boot/dts/loongson/rs780e-pch.dtsi b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
index 8687c4f7370a..d0d5d60a8697 100644
--- a/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
+++ b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
@@ -9,6 +9,18 @@ bus@10000000 {
 				0 0x40000000 0 0x40000000 0 0x40000000
 				0xfd 0xfe000000 0xfd 0xfe000000  0 0x2000000 /* PCI Config Space */>;
 
+		pci@1a000000 {
+			compatible = "loongson,rs780e-pci";
+			device_type = "pci";
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			reg = <0 0x1a000000 0 0x02000000>;
+
+			ranges = <0x01000000 0 0x00004000 0 0x18004000 0 0x00004000>,
+				 <0x02000000 0 0x40000000 0 0x40000000 0 0x40000000>;
+		};
+
 		isa {
 			compatible = "isa";
 			#address-cells = <2>;
-- 
2.26.0.rc2


^ permalink raw reply related	[flat|nested] 63+ messages in thread

* [PATCH v6 5/5] MIPS: Loongson64: Switch to generic PCI driver
  2020-04-27  6:05 [PATCH v6 0/5] Loongson PCI Generic Driver Jiaxun Yang
                   ` (3 preceding siblings ...)
  2020-04-27  6:05 ` [PATCH v6 4/5] MIPS: DTS: Loongson64: Add PCI Controller Node Jiaxun Yang
@ 2020-04-27  6:05 ` Jiaxun Yang
  2020-04-28  1:14 ` [PATCH v7 0/5] Loongson PCI Generic Driver Jiaxun Yang
                   ` (4 subsequent siblings)
  9 siblings, 0 replies; 63+ messages in thread
From: Jiaxun Yang @ 2020-04-27  6:05 UTC (permalink / raw)
  To: linux-mips
  Cc: Jiaxun Yang, Bjorn Helgaas, Rob Herring, Thomas Bogendoerfer,
	Huacai Chen, Lorenzo Pieralisi, Paul Burton, linux-pci,
	devicetree, linux-kernel

We can now enable generic PCI driver in Kconfig, and remove legacy
PCI driver code.

Radeon vbios quirk is moved to the platform folder to fit the
new structure.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 arch/mips/Kconfig                  |   1 +
 arch/mips/loongson64/Makefile      |   2 +-
 arch/mips/loongson64/vbios_quirk.c |  29 ++++++++
 arch/mips/pci/Makefile             |   1 -
 arch/mips/pci/fixup-loongson3.c    |  71 ------------------
 arch/mips/pci/ops-loongson3.c      | 116 -----------------------------
 6 files changed, 31 insertions(+), 189 deletions(-)
 create mode 100644 arch/mips/loongson64/vbios_quirk.c
 delete mode 100644 arch/mips/pci/fixup-loongson3.c
 delete mode 100644 arch/mips/pci/ops-loongson3.c

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 0519ca9f00f9..7a4fcc4ade1f 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -480,6 +480,7 @@ config MACH_LOONGSON64
 	select IRQ_MIPS_CPU
 	select NR_CPUS_DEFAULT_64
 	select USE_GENERIC_EARLY_PRINTK_8250
+	select PCI_DRIVERS_GENERIC
 	select SYS_HAS_CPU_LOONGSON64
 	select SYS_HAS_EARLY_PRINTK
 	select SYS_SUPPORTS_SMP
diff --git a/arch/mips/loongson64/Makefile b/arch/mips/loongson64/Makefile
index 6f3c2b47f66f..6f81b822aeae 100644
--- a/arch/mips/loongson64/Makefile
+++ b/arch/mips/loongson64/Makefile
@@ -8,5 +8,5 @@ obj-$(CONFIG_MACH_LOONGSON64) += cop2-ex.o platform.o dma.o \
 obj-$(CONFIG_SMP)	+= smp.o
 obj-$(CONFIG_NUMA)	+= numa.o
 obj-$(CONFIG_RS780_HPET) += hpet.o
-obj-$(CONFIG_PCI) += pci.o
 obj-$(CONFIG_SUSPEND) += pm.o
+obj-$(CONFIG_PCI_QUIRKS) += vbios_quirk.o
diff --git a/arch/mips/loongson64/vbios_quirk.c b/arch/mips/loongson64/vbios_quirk.c
new file mode 100644
index 000000000000..1f0a462aeddd
--- /dev/null
+++ b/arch/mips/loongson64/vbios_quirk.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <linux/pci.h>
+#include <loongson.h>
+
+static void pci_fixup_radeon(struct pci_dev *pdev)
+{
+	struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
+
+	if (res->start)
+		return;
+
+	if (!loongson_sysconf.vgabios_addr)
+		return;
+
+	pci_disable_rom(pdev);
+	if (res->parent)
+		release_resource(res);
+
+	res->start = virt_to_phys((void *) loongson_sysconf.vgabios_addr);
+	res->end   = res->start + 256*1024 - 1;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ROM_SHADOW |
+		     IORESOURCE_PCI_FIXED;
+
+	dev_info(&pdev->dev, "BAR %d: assigned %pR for Radeon ROM\n",
+		 PCI_ROM_RESOURCE, res);
+}
+DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, 0x9615,
+				PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_radeon);
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 342ce10ef593..438f10955d89 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -35,7 +35,6 @@ obj-$(CONFIG_LASAT)		+= pci-lasat.o
 obj-$(CONFIG_MIPS_COBALT)	+= fixup-cobalt.o
 obj-$(CONFIG_LEMOTE_FULOONG2E)	+= fixup-fuloong2e.o ops-loongson2.o
 obj-$(CONFIG_LEMOTE_MACH2F)	+= fixup-lemote2f.o ops-loongson2.o
-obj-$(CONFIG_MACH_LOONGSON64)	+= fixup-loongson3.o ops-loongson3.o
 obj-$(CONFIG_MIPS_MALTA)	+= fixup-malta.o pci-malta.o
 obj-$(CONFIG_PMC_MSP7120_GW)	+= fixup-pmcmsp.o ops-pmcmsp.o
 obj-$(CONFIG_PMC_MSP7120_EVAL)	+= fixup-pmcmsp.o ops-pmcmsp.o
diff --git a/arch/mips/pci/fixup-loongson3.c b/arch/mips/pci/fixup-loongson3.c
deleted file mode 100644
index 8a741c2c6685..000000000000
--- a/arch/mips/pci/fixup-loongson3.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * fixup-loongson3.c
- *
- * Copyright (C) 2012 Lemote, Inc.
- * Author: Xiang Yu, xiangy@lemote.com
- *         Chen Huacai, chenhc@lemote.com
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- * THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- * WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- * NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- * USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-
-#include <linux/pci.h>
-#include <boot_param.h>
-
-static void print_fixup_info(const struct pci_dev *pdev)
-{
-	dev_info(&pdev->dev, "Device %x:%x, irq %d\n",
-			pdev->vendor, pdev->device, pdev->irq);
-}
-
-int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
-	print_fixup_info(dev);
-	return dev->irq;
-}
-
-static void pci_fixup_radeon(struct pci_dev *pdev)
-{
-	struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
-
-	if (res->start)
-		return;
-
-	if (!loongson_sysconf.vgabios_addr)
-		return;
-
-	pci_disable_rom(pdev);
-	if (res->parent)
-		release_resource(res);
-
-	res->start = virt_to_phys((void *) loongson_sysconf.vgabios_addr);
-	res->end   = res->start + 256*1024 - 1;
-	res->flags = IORESOURCE_MEM | IORESOURCE_ROM_SHADOW |
-		     IORESOURCE_PCI_FIXED;
-
-	dev_info(&pdev->dev, "BAR %d: assigned %pR for Radeon ROM\n",
-		 PCI_ROM_RESOURCE, res);
-}
-
-DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
-				PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_radeon);
-
-/* Do platform specific device initialization at pci_enable_device() time */
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
-	return 0;
-}
diff --git a/arch/mips/pci/ops-loongson3.c b/arch/mips/pci/ops-loongson3.c
deleted file mode 100644
index 2f6ad36bdea6..000000000000
--- a/arch/mips/pci/ops-loongson3.c
+++ /dev/null
@@ -1,116 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-
-#include <asm/mips-boards/bonito64.h>
-
-#include <loongson.h>
-
-#define PCI_ACCESS_READ  0
-#define PCI_ACCESS_WRITE 1
-
-#define HT1LO_PCICFG_BASE      0x1a000000
-#define HT1LO_PCICFG_BASE_TP1  0x1b000000
-
-static int loongson3_pci_config_access(unsigned char access_type,
-		struct pci_bus *bus, unsigned int devfn,
-		int where, u32 *data)
-{
-	unsigned char busnum = bus->number;
-	int function = PCI_FUNC(devfn);
-	int device = PCI_SLOT(devfn);
-	int reg = where & ~3;
-	void *addrp;
-	u64 addr;
-
-	if (where < PCI_CFG_SPACE_SIZE) { /* standard config */
-		addr = (busnum << 16) | (device << 11) | (function << 8) | reg;
-		if (busnum == 0) {
-			if (device > 31)
-				return PCIBIOS_DEVICE_NOT_FOUND;
-			addrp = (void *)TO_UNCAC(HT1LO_PCICFG_BASE | addr);
-		} else {
-			addrp = (void *)TO_UNCAC(HT1LO_PCICFG_BASE_TP1 | addr);
-		}
-	} else if (where < PCI_CFG_SPACE_EXP_SIZE) {  /* extended config */
-		struct pci_dev *rootdev;
-
-		rootdev = pci_get_domain_bus_and_slot(0, 0, 0);
-		if (!rootdev)
-			return PCIBIOS_DEVICE_NOT_FOUND;
-
-		addr = pci_resource_start(rootdev, 3);
-		if (!addr)
-			return PCIBIOS_DEVICE_NOT_FOUND;
-
-		addr |= busnum << 20 | device << 15 | function << 12 | reg;
-		addrp = (void *)TO_UNCAC(addr);
-	} else {
-		return PCIBIOS_DEVICE_NOT_FOUND;
-	}
-
-	if (access_type == PCI_ACCESS_WRITE)
-		writel(*data, addrp);
-	else {
-		*data = readl(addrp);
-		if (*data == 0xffffffff) {
-			*data = -1;
-			return PCIBIOS_DEVICE_NOT_FOUND;
-		}
-	}
-	return PCIBIOS_SUCCESSFUL;
-}
-
-static int loongson3_pci_pcibios_read(struct pci_bus *bus, unsigned int devfn,
-				 int where, int size, u32 *val)
-{
-	u32 data = 0;
-	int ret = loongson3_pci_config_access(PCI_ACCESS_READ,
-			bus, devfn, where, &data);
-
-	if (ret != PCIBIOS_SUCCESSFUL)
-		return ret;
-
-	if (size == 1)
-		*val = (data >> ((where & 3) << 3)) & 0xff;
-	else if (size == 2)
-		*val = (data >> ((where & 3) << 3)) & 0xffff;
-	else
-		*val = data;
-
-	return PCIBIOS_SUCCESSFUL;
-}
-
-static int loongson3_pci_pcibios_write(struct pci_bus *bus, unsigned int devfn,
-				  int where, int size, u32 val)
-{
-	u32 data = 0;
-	int ret;
-
-	if (size == 4)
-		data = val;
-	else {
-		ret = loongson3_pci_config_access(PCI_ACCESS_READ,
-				bus, devfn, where, &data);
-		if (ret != PCIBIOS_SUCCESSFUL)
-			return ret;
-
-		if (size == 1)
-			data = (data & ~(0xff << ((where & 3) << 3))) |
-			    (val << ((where & 3) << 3));
-		else if (size == 2)
-			data = (data & ~(0xffff << ((where & 3) << 3))) |
-			    (val << ((where & 3) << 3));
-	}
-
-	ret = loongson3_pci_config_access(PCI_ACCESS_WRITE,
-			bus, devfn, where, &data);
-
-	return ret;
-}
-
-struct pci_ops loongson_pci_ops = {
-	.read = loongson3_pci_pcibios_read,
-	.write = loongson3_pci_pcibios_write
-};
-- 
2.26.0.rc2


^ permalink raw reply related	[flat|nested] 63+ messages in thread

* Re: [PATCH v6 2/5] PCI: Add Loongson PCI Controller support
  2020-04-27  6:05 ` [PATCH v6 2/5] PCI: Add Loongson PCI Controller support Jiaxun Yang
@ 2020-04-27  6:29   ` Huacai Chen
  2020-04-27  6:46     ` Jiaxun Yang
  0 siblings, 1 reply; 63+ messages in thread
From: Huacai Chen @ 2020-04-27  6:29 UTC (permalink / raw)
  To: Jiaxun Yang
  Cc: open list:MIPS, Bjorn Helgaas, Rob Herring, Thomas Bogendoerfer,
	Lorenzo Pieralisi, Paul Burton, linux-pci, devicetree, LKML

Hi, Jiaxun,

On Mon, Apr 27, 2020 at 2:06 PM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>
> This controller can be found on Loongson-2K SoC, Loongson-3
> systems with RS780E/LS7A PCH.
>
> The RS780E part of code was previously located at
> arch/mips/pci/ops-loongson3.c and now it can use generic PCI
> driver implementation.
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>
> --
> v2:
>         - Clean up according to rob's suggestions
>         - Claim that it can't work as a module
> v3:
>         - Fix a typo
> v4:
>         - More clean-ups: Drop flag check, use devfn
> ---
>  drivers/pci/controller/Kconfig        |  10 +
>  drivers/pci/controller/Makefile       |   1 +
>  drivers/pci/controller/pci-loongson.c | 251 ++++++++++++++++++++++++++
>  3 files changed, 262 insertions(+)
>  create mode 100644 drivers/pci/controller/pci-loongson.c
>
> diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> index 91bfdb784829..ae36edb1d7db 100644
> --- a/drivers/pci/controller/Kconfig
> +++ b/drivers/pci/controller/Kconfig
> @@ -258,6 +258,16 @@ config PCI_HYPERV_INTERFACE
>           The Hyper-V PCI Interface is a helper driver allows other drivers to
>           have a common interface with the Hyper-V PCI frontend driver.
>
> +config PCI_LOONGSON
> +       bool "LOONGSON PCI Controller"
> +       depends on MACH_LOONGSON64 || COMPILE_TEST
> +       depends on OF
> +       depends on PCI_QUIRKS
> +       default MACH_LOONGSON64
> +       help
> +         Say Y here if you want to enable PCI controller support on
> +         Loongson systems.
> +
>  source "drivers/pci/controller/dwc/Kconfig"
>  source "drivers/pci/controller/mobiveil/Kconfig"
>  source "drivers/pci/controller/cadence/Kconfig"
> diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
> index 158c59771824..fbac4b0190a0 100644
> --- a/drivers/pci/controller/Makefile
> +++ b/drivers/pci/controller/Makefile
> @@ -28,6 +28,7 @@ obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
>  obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
>  obj-$(CONFIG_VMD) += vmd.o
>  obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
> +obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o
>  # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
>  obj-y                          += dwc/
>  obj-y                          += mobiveil/
> diff --git a/drivers/pci/controller/pci-loongson.c b/drivers/pci/controller/pci-loongson.c
> new file mode 100644
> index 000000000000..6cb8de384d36
> --- /dev/null
> +++ b/drivers/pci/controller/pci-loongson.c
> @@ -0,0 +1,251 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Loongson PCI Host Controller Driver
> + *
> + * Copyright (C) 2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
> + */
> +
> +#include <linux/of_device.h>
> +#include <linux/of_pci.h>
> +#include <linux/pci.h>
> +#include <linux/pci_ids.h>
> +
> +#include "../pci.h"
> +
> +/* Device IDs */
> +#define DEV_PCIE_PORT_0        0x7a09
> +#define DEV_PCIE_PORT_1        0x7a19
> +#define DEV_PCIE_PORT_2        0x7a29
> +
> +#define DEV_LS2K_APB   0x7a02
> +#define DEV_LS7A_CONF  0x7a10
> +#define DEV_LS7A_LPC   0x7a0c
> +
> +#define FLAG_CFG0      BIT(0)
> +#define FLAG_CFG1      BIT(1)
> +#define FLAG_DEV_FIX   BIT(2)
> +
> +struct loongson_pci {
> +       void __iomem *cfg0_base;
> +       void __iomem *cfg1_base;
> +       struct platform_device *pdev;
> +       u32 flags;
> +};
> +
> +/* Fixup wrong class code in PCIe bridges */
> +static void bridge_class_quirk(struct pci_dev *dev)
> +{
> +       dev->class = PCI_CLASS_BRIDGE_PCI << 8;
> +}
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON,
> +                       DEV_PCIE_PORT_0, bridge_class_quirk);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON,
> +                       DEV_PCIE_PORT_1, bridge_class_quirk);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON,
> +                       DEV_PCIE_PORT_2, bridge_class_quirk);
> +
> +static void system_bus_quirk(struct pci_dev *pdev)
> +{
> +       u16 tmp;
> +
> +       pdev->mmio_always_on = 1;
> +       pdev->non_compliant_bars = 1;
> +       /* Enable MEM & IO Decoding */
> +       pci_read_config_word(pdev, PCI_STATUS, &tmp);
> +       tmp |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
> +       pci_write_config_word(pdev, PCI_STATUS, tmp);
> +}
> +
> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
> +                       DEV_LS2K_APB, system_bus_quirk);
> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
> +                       DEV_LS7A_CONF, system_bus_quirk);
> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
> +                       DEV_LS7A_LPC, system_bus_quirk);
> +
> +static void loongson_mrrs_quirk(struct pci_dev *dev)
> +{
> +       struct pci_bus *bus = dev->bus;
> +       struct pci_dev *bridge;
> +       static const struct pci_device_id bridge_devids[] = {
> +               { PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_0) },
> +               { PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_1) },
> +               { PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_2) },
> +               { 0, },
> +       };
> +
> +
> +       /* look for the matching bridge */
> +       while (!pci_is_root_bus(bus)) {
> +               bridge = bus->self;
> +               bus = bus->parent;
> +               /*
> +                * Some Loongson PCIE ports has a h/w limitation of
> +                * 256 bytes maximum read request size. It can't handle
> +                * anything higher than this. So force this limit on
> +                * any devices attached under these ports.
> +                */
> +               if (pci_match_id(bridge_devids, bridge)) {
> +                       if (pcie_get_readrq(dev) > 256) {
> +                               dev_info(&dev->dev, "limiting MRRS to 256\n");
> +                               pcie_set_readrq(dev, 256);
> +                       }
> +                       break;
> +               }
> +       }
> +}
> +DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, loongson_mrrs_quirk);
> +
> +static void __iomem *cfg1_map(struct loongson_pci *priv, int bus,
> +                               unsigned int devfn, int where)
> +{
> +       unsigned long addroff = 0x0;
> +
> +       if (bus != 0)
> +               addroff |= BIT(28); /* Type 1 Access */
> +       addroff |= (where & 0xff) | ((where & 0xf00) << 16);
> +       addroff |= (bus << 16) | (devfn << 8);
> +       return priv->cfg1_base + addroff;
> +}
> +
> +static void __iomem *cfg0_map(struct loongson_pci *priv, int bus,
> +                               unsigned int devfn, int where)
> +{
> +       unsigned long addroff = 0x0;
> +
> +       if (bus != 0)
> +               addroff |= BIT(24); /* Type 1 Access */
> +       addroff |= (bus << 16) | (devfn << 8) | where;
> +       return priv->cfg0_base + addroff;
> +}
> +
> +void __iomem *pci_loongson_map_bus(struct pci_bus *bus, unsigned int devfn,
> +                              int where)
> +{
> +       unsigned char busnum = bus->number;
> +       struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
> +       struct loongson_pci *priv =  pci_host_bridge_priv(bridge);
> +
> +       /*
> +        * Do not read more than one device on the bus other than
> +        * the host bridge.
> +        */
> +       if (bus->primary != 0 && PCI_SLOT(devfn) > 0 &&
> +               priv->flags & FLAG_DEV_FIX)
> +               return NULL;
> +
> +       /* CFG0 can only access standard space */
> +       if (where < PCI_CFG_SPACE_SIZE && priv->cfg0_base)
> +               return cfg0_map(priv, busnum, devfn, where);
> +
> +       /* CFG1 can access extended space */
> +       if (where < PCI_CFG_SPACE_EXP_SIZE && priv->cfg1_base)
> +               return cfg1_map(priv, busnum, devfn, where);
> +
> +       return NULL;
> +}
> +
> +static int loongson_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
> +{
> +       int irq;
> +       u8 val;
> +
> +       irq = of_irq_parse_and_map_pci(dev, slot, pin);
> +       if (irq > 0)
> +               return irq;
> +
> +       /* Care i8259 legacy systems */
> +       pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &val);
> +       /* i8259 only have 15 IRQs */
> +       if (val > 15)
> +               return 0;
> +
> +       return val;
> +}
> +
> +/* H/w only accept 32-bit PCI operations */
> +static struct pci_ops loongson_pci_ops = {
> +       .map_bus = pci_loongson_map_bus,
> +       .read   = pci_generic_config_read32,
> +       .write  = pci_generic_config_write32,
> +};
> +
> +static const struct of_device_id loongson_pci_of_match[] = {
> +       { .compatible = "loongson,rs780e-pci",
> +               .data = (void *)(FLAG_CFG0), },
> +       { .compatible = "loongson,ls2k-pci",
> +               .data = (void *)(FLAG_CFG0 | FLAG_CFG1 | FLAG_DEV_FIX), },
> +       { .compatible = "loongson,ls7a-pci",
> +               .data = (void *)(FLAG_CFG0 | FLAG_CFG1 | FLAG_DEV_FIX), },
I suggest to use alpha-betical order here: ls2k, ls7a and rs780 at last.

> +       {}
> +};
> +
> +static int loongson_pci_probe(struct platform_device *pdev)
> +{
> +       struct loongson_pci *priv;
> +       struct device *dev = &pdev->dev;
> +       struct device_node *node = dev->of_node;
> +       struct pci_host_bridge *bridge;
> +       struct resource *regs;
> +       int err;
> +
> +       if (!node)
> +               return -ENODEV;
> +
> +       bridge = devm_pci_alloc_host_bridge(dev, sizeof(*priv));
> +       if (!bridge)
> +               return -ENODEV;
> +
> +       priv = pci_host_bridge_priv(bridge);
> +       priv->pdev = pdev;
> +       priv->flags = (unsigned long)of_device_get_match_data(dev);
> +
> +       regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +       if (!regs) {
> +               dev_err(dev, "missing mem resources for cfg0\n");
> +               return -EINVAL;
> +       }
> +
> +       priv->cfg0_base = devm_pci_remap_cfg_resource(dev, regs);
> +       if (IS_ERR(priv->cfg0_base))
> +               return PTR_ERR(priv->cfg0_base);
> +
> +       /* CFG1 is optional */
> +       if (priv->flags & FLAG_CFG1) {
> +               regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> +               if (!regs)
> +                       dev_info(dev, "missing mem resource for cfg1\n");
> +               else {
> +                       priv->cfg1_base = devm_pci_remap_cfg_resource(dev, regs);
> +                       if (IS_ERR(priv->cfg1_base))
> +                               priv->cfg1_base = NULL;
> +               }
> +       }
> +
> +       err = pci_parse_request_of_pci_ranges(dev, &bridge->windows,
> +                                               &bridge->dma_ranges, NULL);
> +       if (err) {
> +               dev_err(dev, "Failed to get bridge resources\n");
> +               return err;
> +       }
> +
> +       bridge->dev.parent = dev;
> +       bridge->sysdata = priv;
> +       bridge->ops = &loongson_pci_ops;
> +       bridge->map_irq = loongson_map_irq;
> +
> +       err = pci_host_probe(bridge);
> +       if (err)
> +               return err;
> +
> +       return 0;
> +}
> +
> +static struct platform_driver loongson_pci_driver = {
> +       .driver = {
> +               .name = "loongson-pci",
> +               .of_match_table = loongson_pci_of_match,
> +       },
> +       .probe = loongson_pci_probe,
> +};
> +builtin_platform_driver(loongson_pci_driver);
> --
> 2.26.0.rc2
>
Thanks,
Huacai

^ permalink raw reply	[flat|nested] 63+ messages in thread

* Re: [PATCH v6 2/5] PCI: Add Loongson PCI Controller support
  2020-04-27  6:29   ` Huacai Chen
@ 2020-04-27  6:46     ` Jiaxun Yang
  0 siblings, 0 replies; 63+ messages in thread
From: Jiaxun Yang @ 2020-04-27  6:46 UTC (permalink / raw)
  To: Huacai Chen
  Cc: open list:MIPS, Bjorn Helgaas, Rob Herring, Thomas Bogendoerfer,
	Lorenzo Pieralisi, Paul Burton, linux-pci, devicetree, LKML

On Mon, 27 Apr 2020 14:29:34 +0800
Huacai Chen <chenhc@lemote.com> wrote:

> Hi, Jiaxun,
> 
> On Mon, Apr 27, 2020 at 2:06 PM Jiaxun Yang <jiaxun.yang@flygoat.com>
> wrote:
> >
> > This controller can be found on Loongson-2K SoC, Loongson-3
> > systems with RS780E/LS7A PCH.
> >
> > The RS780E part of code was previously located at
> > arch/mips/pci/ops-loongson3.c and now it can use generic PCI
> > driver implementation.
> >
> > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> >
> > --
> > v2:
> >         - Clean up according to rob's suggestions
> >         - Claim that it can't work as a module
> > v3:
> >         - Fix a typo
> > v4:
> >         - More clean-ups: Drop flag check, use devfn
> > ---
> >  drivers/pci/controller/Kconfig        |  10 +
> >  drivers/pci/controller/Makefile       |   1 +
> >  drivers/pci/controller/pci-loongson.c | 251

[...]

> > +static const struct of_device_id loongson_pci_of_match[] = {
> > +       { .compatible = "loongson,rs780e-pci",
> > +               .data = (void *)(FLAG_CFG0), },
> > +       { .compatible = "loongson,ls2k-pci",
> > +               .data = (void *)(FLAG_CFG0 | FLAG_CFG1 |
> > FLAG_DEV_FIX), },
> > +       { .compatible = "loongson,ls7a-pci",
> > +               .data = (void *)(FLAG_CFG0 | FLAG_CFG1 |
> > FLAG_DEV_FIX), },  
> I suggest to use alpha-betical order here: ls2k, ls7a and rs780 at
> last.

Thanks for pointing out this minor issue.
I put rs780e at first at it appears to be the first system using this
driver.
If there is no more review suggestion I'll send out next revision very
soon. 

[...]

--
Jiaxun Yang

^ permalink raw reply	[flat|nested] 63+ messages in thread

* Re: [PATCH v6 1/5] PCI: Don't disable decoding when mmio_always_on is set
  2020-04-27  6:05 ` [PATCH v6 1/5] PCI: Don't disable decoding when mmio_always_on is set Jiaxun Yang
@ 2020-04-27  7:42   ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 63+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-04-27  7:42 UTC (permalink / raw)
  To: Jiaxun Yang
  Cc: open list:BROADCOM NVRAM DRIVER, Bjorn Helgaas, Rob Herring,
	Thomas Bogendoerfer, Huacai Chen, Lorenzo Pieralisi, Paul Burton,
	linux-pci,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	open list

On Mon, Apr 27, 2020 at 8:08 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>
> Don't disable MEM/IO decoing when a device have both non_compliant_bars

Typo "decoing" -> "decoding"

> and mmio_always_on.
>
> That would allow us quirk devices with junk in BARs but can't disable
> their decoding.
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
>  drivers/pci/probe.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> index 77b8a145c39b..d9c2c3301a8a 100644
> --- a/drivers/pci/probe.c
> +++ b/drivers/pci/probe.c
> @@ -1822,7 +1822,7 @@ int pci_setup_device(struct pci_dev *dev)
>         /* Device class may be changed after fixup */
>         class = dev->class >> 8;
>
> -       if (dev->non_compliant_bars) {
> +       if (dev->non_compliant_bars && !dev->mmio_always_on) {
>                 pci_read_config_word(dev, PCI_COMMAND, &cmd);
>                 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
>                         pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
> --
> 2.26.0.rc2
>

^ permalink raw reply	[flat|nested] 63+ messages in thread

* [PATCH v7 0/5] Loongson PCI Generic Driver
  2020-04-27  6:05 [PATCH v6 0/5] Loongson PCI Generic Driver Jiaxun Yang
                   ` (4 preceding siblings ...)
  2020-04-27  6:05 ` [PATCH v6 5/5] MIPS: Loongson64: Switch to generic PCI driver Jiaxun Yang
@ 2020-04-28  1:14 ` Jiaxun Yang
  2020-04-28  1:14   ` [PATCH v7 1/5] PCI: Don't disable decoding when mmio_always_on is set Jiaxun Yang
                     ` (4 more replies)
  2020-05-08 11:34 ` [PATCH v8 1/5] PCI: Don't disable decoding when mmio_always_on is set Jiaxun Yang
                   ` (3 subsequent siblings)
  9 siblings, 5 replies; 63+ messages in thread
From: Jiaxun Yang @ 2020-04-28  1:14 UTC (permalink / raw)
  To: linux-mips
  Cc: Jiaxun Yang, Bjorn Helgaas, Rob Herring, Thomas Bogendoerfer,
	Huacai Chen, Lorenzo Pieralisi, Paul Burton, linux-pci,
	devicetree, linux-kernel

Hi,

This series converts Loongson PCI into a generic PCI controller
driver and adds support for LS2K SoC and LS7A PCH's PCI support.

Is it possible to let patch 1~3 go through PCI tree and patch
4~5 go through MIPS tree?

Thanks.

v6: Drop first the patch of previous versions. Driver code clean-ups
according to rob's suggestion.

It looks like I had a wrong impression on generic IO port handeling
and now the issue has been fixed, I implemented PCI_IOBASE for MIPS[1].
Now the address is uniform here.

[1]: https://patchwork.kernel.org/cover/11510499/

v7: Fix some minor issues.

Jiaxun Yang (5):
  PCI: Don't disable decoding when mmio_always_on is set
  PCI: Add Loongson PCI Controller support
  dt-bindings: Document Loongson PCI Host Controller
  MIPS: DTS: Loongson64: Add PCI Controller Node
  MIPS: Loongson64: Switch to generic PCI driver

 .../devicetree/bindings/pci/loongson.yaml     |  62 +++++
 arch/mips/Kconfig                             |   1 +
 arch/mips/boot/dts/loongson/rs780e-pch.dtsi   |  12 +
 arch/mips/loongson64/Makefile                 |   2 +-
 arch/mips/loongson64/vbios_quirk.c            |  29 ++
 arch/mips/pci/Makefile                        |   1 -
 arch/mips/pci/fixup-loongson3.c               |  71 -----
 arch/mips/pci/ops-loongson3.c                 | 116 --------
 drivers/pci/controller/Kconfig                |  10 +
 drivers/pci/controller/Makefile               |   1 +
 drivers/pci/controller/pci-loongson.c         | 251 ++++++++++++++++++
 drivers/pci/probe.c                           |   2 +-
 12 files changed, 368 insertions(+), 190 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pci/loongson.yaml
 create mode 100644 arch/mips/loongson64/vbios_quirk.c
 delete mode 100644 arch/mips/pci/fixup-loongson3.c
 delete mode 100644 arch/mips/pci/ops-loongson3.c
 create mode 100644 drivers/pci/controller/pci-loongson.c

-- 
2.26.0.rc2


^ permalink raw reply	[flat|nested] 63+ messages in thread

* [PATCH v7 1/5] PCI: Don't disable decoding when mmio_always_on is set
  2020-04-28  1:14 ` [PATCH v7 0/5] Loongson PCI Generic Driver Jiaxun Yang
@ 2020-04-28  1:14   ` Jiaxun Yang
  2020-05-08 18:51     ` Bjorn Helgaas
  2020-05-20 20:55     ` Rob Herring
  2020-04-28  1:14   ` [PATCH v7 2/5] PCI: Add Loongson PCI Controller support Jiaxun Yang
                     ` (3 subsequent siblings)
  4 siblings, 2 replies; 63+ messages in thread
From: Jiaxun Yang @ 2020-04-28  1:14 UTC (permalink / raw)
  To: linux-mips
  Cc: Jiaxun Yang, Bjorn Helgaas, Rob Herring, Thomas Bogendoerfer,
	Huacai Chen, Lorenzo Pieralisi, Paul Burton, linux-pci,
	devicetree, linux-kernel

Don't disable MEM/IO decoding when a device have both non_compliant_bars
and mmio_always_on.

That would allow us quirk devices with junk in BARs but can't disable
their decoding.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 drivers/pci/probe.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 77b8a145c39b..d9c2c3301a8a 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -1822,7 +1822,7 @@ int pci_setup_device(struct pci_dev *dev)
 	/* Device class may be changed after fixup */
 	class = dev->class >> 8;
 
-	if (dev->non_compliant_bars) {
+	if (dev->non_compliant_bars && !dev->mmio_always_on) {
 		pci_read_config_word(dev, PCI_COMMAND, &cmd);
 		if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
 			pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
-- 
2.26.0.rc2


^ permalink raw reply related	[flat|nested] 63+ messages in thread

* [PATCH v7 2/5] PCI: Add Loongson PCI Controller support
  2020-04-28  1:14 ` [PATCH v7 0/5] Loongson PCI Generic Driver Jiaxun Yang
  2020-04-28  1:14   ` [PATCH v7 1/5] PCI: Don't disable decoding when mmio_always_on is set Jiaxun Yang
@ 2020-04-28  1:14   ` Jiaxun Yang
  2020-04-29 18:43     ` Rob Herring
  2020-05-04 23:43     ` Bjorn Helgaas
  2020-04-28  1:14   ` [PATCH v7 3/5] dt-bindings: Document Loongson PCI Host Controller Jiaxun Yang
                     ` (2 subsequent siblings)
  4 siblings, 2 replies; 63+ messages in thread
From: Jiaxun Yang @ 2020-04-28  1:14 UTC (permalink / raw)
  To: linux-mips
  Cc: Jiaxun Yang, Bjorn Helgaas, Rob Herring, Thomas Bogendoerfer,
	Huacai Chen, Lorenzo Pieralisi, Paul Burton, linux-pci,
	devicetree, linux-kernel

This controller can be found on Loongson-2K SoC, Loongson-3
systems with RS780E/LS7A PCH.

The RS780E part of code was previously located at
arch/mips/pci/ops-loongson3.c and now it can use generic PCI
driver implementation.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>

--
v2:
	- Clean up according to rob's suggestions
	- Claim that it can't work as a module
v3:
	- Fix a typo
v4:
	- More clean-ups: Drop flag check, use devfn
v7:
	- Fix ordering according to huacai's suggestion
---
 drivers/pci/controller/Kconfig        |  10 +
 drivers/pci/controller/Makefile       |   1 +
 drivers/pci/controller/pci-loongson.c | 251 ++++++++++++++++++++++++++
 3 files changed, 262 insertions(+)
 create mode 100644 drivers/pci/controller/pci-loongson.c

diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 91bfdb784829..ae36edb1d7db 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -258,6 +258,16 @@ config PCI_HYPERV_INTERFACE
 	  The Hyper-V PCI Interface is a helper driver allows other drivers to
 	  have a common interface with the Hyper-V PCI frontend driver.
 
+config PCI_LOONGSON
+	bool "LOONGSON PCI Controller"
+	depends on MACH_LOONGSON64 || COMPILE_TEST
+	depends on OF
+	depends on PCI_QUIRKS
+	default MACH_LOONGSON64
+	help
+	  Say Y here if you want to enable PCI controller support on
+	  Loongson systems.
+
 source "drivers/pci/controller/dwc/Kconfig"
 source "drivers/pci/controller/mobiveil/Kconfig"
 source "drivers/pci/controller/cadence/Kconfig"
diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
index 158c59771824..fbac4b0190a0 100644
--- a/drivers/pci/controller/Makefile
+++ b/drivers/pci/controller/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
 obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
 obj-$(CONFIG_VMD) += vmd.o
 obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
+obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o
 # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
 obj-y				+= dwc/
 obj-y				+= mobiveil/
diff --git a/drivers/pci/controller/pci-loongson.c b/drivers/pci/controller/pci-loongson.c
new file mode 100644
index 000000000000..db1ebf42faf3
--- /dev/null
+++ b/drivers/pci/controller/pci-loongson.c
@@ -0,0 +1,251 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Loongson PCI Host Controller Driver
+ *
+ * Copyright (C) 2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
+ */
+
+#include <linux/of_device.h>
+#include <linux/of_pci.h>
+#include <linux/pci.h>
+#include <linux/pci_ids.h>
+
+#include "../pci.h"
+
+/* Device IDs */
+#define DEV_PCIE_PORT_0	0x7a09
+#define DEV_PCIE_PORT_1	0x7a19
+#define DEV_PCIE_PORT_2	0x7a29
+
+#define DEV_LS2K_APB	0x7a02
+#define DEV_LS7A_CONF	0x7a10
+#define DEV_LS7A_LPC	0x7a0c
+
+#define FLAG_CFG0	BIT(0)
+#define FLAG_CFG1	BIT(1)
+#define FLAG_DEV_FIX	BIT(2)
+
+struct loongson_pci {
+	void __iomem *cfg0_base;
+	void __iomem *cfg1_base;
+	struct platform_device *pdev;
+	u32 flags;
+};
+
+/* Fixup wrong class code in PCIe bridges */
+static void bridge_class_quirk(struct pci_dev *dev)
+{
+	dev->class = PCI_CLASS_BRIDGE_PCI << 8;
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON,
+			DEV_PCIE_PORT_0, bridge_class_quirk);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON,
+			DEV_PCIE_PORT_1, bridge_class_quirk);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON,
+			DEV_PCIE_PORT_2, bridge_class_quirk);
+
+static void system_bus_quirk(struct pci_dev *pdev)
+{
+	u16 tmp;
+
+	pdev->mmio_always_on = 1;
+	pdev->non_compliant_bars = 1;
+	/* Enable MEM & IO Decoding */
+	pci_read_config_word(pdev, PCI_STATUS, &tmp);
+	tmp |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
+	pci_write_config_word(pdev, PCI_STATUS, tmp);
+}
+
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
+			DEV_LS2K_APB, system_bus_quirk);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
+			DEV_LS7A_CONF, system_bus_quirk);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
+			DEV_LS7A_LPC, system_bus_quirk);
+
+static void loongson_mrrs_quirk(struct pci_dev *dev)
+{
+	struct pci_bus *bus = dev->bus;
+	struct pci_dev *bridge;
+	static const struct pci_device_id bridge_devids[] = {
+		{ PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_0) },
+		{ PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_1) },
+		{ PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_2) },
+		{ 0, },
+	};
+
+
+	/* look for the matching bridge */
+	while (!pci_is_root_bus(bus)) {
+		bridge = bus->self;
+		bus = bus->parent;
+		/*
+		 * Some Loongson PCIE ports has a h/w limitation of
+		 * 256 bytes maximum read request size. It can't handle
+		 * anything higher than this. So force this limit on
+		 * any devices attached under these ports.
+		 */
+		if (pci_match_id(bridge_devids, bridge)) {
+			if (pcie_get_readrq(dev) > 256) {
+				dev_info(&dev->dev, "limiting MRRS to 256\n");
+				pcie_set_readrq(dev, 256);
+			}
+			break;
+		}
+	}
+}
+DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, loongson_mrrs_quirk);
+
+static void __iomem *cfg1_map(struct loongson_pci *priv, int bus,
+				unsigned int devfn, int where)
+{
+	unsigned long addroff = 0x0;
+
+	if (bus != 0)
+		addroff |= BIT(28); /* Type 1 Access */
+	addroff |= (where & 0xff) | ((where & 0xf00) << 16);
+	addroff |= (bus << 16) | (devfn << 8);
+	return priv->cfg1_base + addroff;
+}
+
+static void __iomem *cfg0_map(struct loongson_pci *priv, int bus,
+				unsigned int devfn, int where)
+{
+	unsigned long addroff = 0x0;
+
+	if (bus != 0)
+		addroff |= BIT(24); /* Type 1 Access */
+	addroff |= (bus << 16) | (devfn << 8) | where;
+	return priv->cfg0_base + addroff;
+}
+
+void __iomem *pci_loongson_map_bus(struct pci_bus *bus, unsigned int devfn,
+			       int where)
+{
+	unsigned char busnum = bus->number;
+	struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
+	struct loongson_pci *priv =  pci_host_bridge_priv(bridge);
+
+	/*
+	 * Do not read more than one device on the bus other than
+	 * the host bridge.
+	 */
+	if (bus->primary != 0 && PCI_SLOT(devfn) > 0 &&
+		priv->flags & FLAG_DEV_FIX)
+		return NULL;
+
+	/* CFG0 can only access standard space */
+	if (where < PCI_CFG_SPACE_SIZE && priv->cfg0_base)
+		return cfg0_map(priv, busnum, devfn, where);
+
+	/* CFG1 can access extended space */
+	if (where < PCI_CFG_SPACE_EXP_SIZE && priv->cfg1_base)
+		return cfg1_map(priv, busnum, devfn, where);
+
+	return NULL;
+}
+
+static int loongson_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+	int irq;
+	u8 val;
+
+	irq = of_irq_parse_and_map_pci(dev, slot, pin);
+	if (irq > 0)
+		return irq;
+
+	/* Care i8259 legacy systems */
+	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &val);
+	/* i8259 only have 15 IRQs */
+	if (val > 15)
+		return 0;
+
+	return val;
+}
+
+/* H/w only accept 32-bit PCI operations */
+static struct pci_ops loongson_pci_ops = {
+	.map_bus = pci_loongson_map_bus,
+	.read	= pci_generic_config_read32,
+	.write	= pci_generic_config_write32,
+};
+
+static const struct of_device_id loongson_pci_of_match[] = {
+	{ .compatible = "loongson,ls2k-pci",
+		.data = (void *)(FLAG_CFG0 | FLAG_CFG1 | FLAG_DEV_FIX), },
+	{ .compatible = "loongson,ls7a-pci",
+		.data = (void *)(FLAG_CFG0 | FLAG_CFG1 | FLAG_DEV_FIX), },
+	{ .compatible = "loongson,rs780e-pci",
+		.data = (void *)(FLAG_CFG0), },
+	{}
+};
+
+static int loongson_pci_probe(struct platform_device *pdev)
+{
+	struct loongson_pci *priv;
+	struct device *dev = &pdev->dev;
+	struct device_node *node = dev->of_node;
+	struct pci_host_bridge *bridge;
+	struct resource *regs;
+	int err;
+
+	if (!node)
+		return -ENODEV;
+
+	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*priv));
+	if (!bridge)
+		return -ENODEV;
+
+	priv = pci_host_bridge_priv(bridge);
+	priv->pdev = pdev;
+	priv->flags = (unsigned long)of_device_get_match_data(dev);
+
+	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!regs) {
+		dev_err(dev, "missing mem resources for cfg0\n");
+		return -EINVAL;
+	}
+
+	priv->cfg0_base = devm_pci_remap_cfg_resource(dev, regs);
+	if (IS_ERR(priv->cfg0_base))
+		return PTR_ERR(priv->cfg0_base);
+
+	/* CFG1 is optional */
+	if (priv->flags & FLAG_CFG1) {
+		regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+		if (!regs)
+			dev_info(dev, "missing mem resource for cfg1\n");
+		else {
+			priv->cfg1_base = devm_pci_remap_cfg_resource(dev, regs);
+			if (IS_ERR(priv->cfg1_base))
+				priv->cfg1_base = NULL;
+		}
+	}
+
+	err = pci_parse_request_of_pci_ranges(dev, &bridge->windows,
+						&bridge->dma_ranges, NULL);
+	if (err) {
+		dev_err(dev, "Failed to get bridge resources\n");
+		return err;
+	}
+
+	bridge->dev.parent = dev;
+	bridge->sysdata = priv;
+	bridge->ops = &loongson_pci_ops;
+	bridge->map_irq = loongson_map_irq;
+
+	err = pci_host_probe(bridge);
+	if (err)
+		return err;
+
+	return 0;
+}
+
+static struct platform_driver loongson_pci_driver = {
+	.driver = {
+		.name = "loongson-pci",
+		.of_match_table = loongson_pci_of_match,
+	},
+	.probe = loongson_pci_probe,
+};
+builtin_platform_driver(loongson_pci_driver);
-- 
2.26.0.rc2


^ permalink raw reply related	[flat|nested] 63+ messages in thread

* [PATCH v7 3/5] dt-bindings: Document Loongson PCI Host Controller
  2020-04-28  1:14 ` [PATCH v7 0/5] Loongson PCI Generic Driver Jiaxun Yang
  2020-04-28  1:14   ` [PATCH v7 1/5] PCI: Don't disable decoding when mmio_always_on is set Jiaxun Yang
  2020-04-28  1:14   ` [PATCH v7 2/5] PCI: Add Loongson PCI Controller support Jiaxun Yang
@ 2020-04-28  1:14   ` Jiaxun Yang
  2020-04-28  1:14   ` [PATCH v7 4/5] MIPS: DTS: Loongson64: Add PCI Controller Node Jiaxun Yang
  2020-04-28  1:14   ` [PATCH v7 5/5] MIPS: Loongson64: Switch to generic PCI driver Jiaxun Yang
  4 siblings, 0 replies; 63+ messages in thread
From: Jiaxun Yang @ 2020-04-28  1:14 UTC (permalink / raw)
  To: linux-mips
  Cc: Jiaxun Yang, Rob Herring, Bjorn Helgaas, Rob Herring,
	Thomas Bogendoerfer, Huacai Chen, Lorenzo Pieralisi, Paul Burton,
	linux-pci, devicetree, linux-kernel

PCI host controller found on Loongson PCHs and SoCs.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../devicetree/bindings/pci/loongson.yaml     | 62 +++++++++++++++++++
 1 file changed, 62 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/loongson.yaml

diff --git a/Documentation/devicetree/bindings/pci/loongson.yaml b/Documentation/devicetree/bindings/pci/loongson.yaml
new file mode 100644
index 000000000000..30e7cf1aeb87
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/loongson.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/loongson.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Loongson PCI Host Controller
+
+maintainers:
+  - Jiaxun Yang <jiaxun.yang@flygoat.com>
+
+description: |+
+  PCI host controller found on Loongson PCHs and SoCs.
+
+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+  compatible:
+    oneOf:
+      - const: loongson,ls2k-pci
+      - const: loongson,ls7a-pci
+      - const: loongson,rs780e-pci
+
+  reg:
+    minItems: 1
+    maxItems: 2
+    items:
+      - description: CFG0 standard config space register
+      - description: CFG1 extended config space register
+
+  ranges:
+    minItems: 1
+    maxItems: 3
+
+
+required:
+  - compatible
+  - reg
+  - ranges
+
+examples:
+  - |
+
+    bus {
+        #address-cells = <2>;
+        #size-cells = <2>;
+        pcie@1a000000 {
+            compatible = "loongson,rs780e-pci";
+            device_type = "pci";
+            #address-cells = <3>;
+            #size-cells = <2>;
+
+            // CPU_PHYSICAL(2)  SIZE(2)
+            reg = <0x0 0x1a000000  0x0 0x2000000>;
+
+            // BUS_ADDRESS(3)  CPU_PHYSICAL(2)  SIZE(2)
+            ranges = <0x01000000 0x0 0x00004000  0x0 0x00004000  0x0 0x00004000>,
+                     <0x02000000 0x0 0x40000000  0x0 0x40000000  0x0 0x40000000>;
+        };
+    };
+...
-- 
2.26.0.rc2


^ permalink raw reply related	[flat|nested] 63+ messages in thread

* [PATCH v7 4/5] MIPS: DTS: Loongson64: Add PCI Controller Node
  2020-04-28  1:14 ` [PATCH v7 0/5] Loongson PCI Generic Driver Jiaxun Yang
                     ` (2 preceding siblings ...)
  2020-04-28  1:14   ` [PATCH v7 3/5] dt-bindings: Document Loongson PCI Host Controller Jiaxun Yang
@ 2020-04-28  1:14   ` Jiaxun Yang
  2020-04-28  1:14   ` [PATCH v7 5/5] MIPS: Loongson64: Switch to generic PCI driver Jiaxun Yang
  4 siblings, 0 replies; 63+ messages in thread
From: Jiaxun Yang @ 2020-04-28  1:14 UTC (permalink / raw)
  To: linux-mips
  Cc: Jiaxun Yang, Bjorn Helgaas, Rob Herring, Thomas Bogendoerfer,
	Huacai Chen, Lorenzo Pieralisi, Paul Burton, linux-pci,
	devicetree, linux-kernel

Add PCI Host controller node for Loongson64 with RS780E PCH dts.
Note that PCI interrupts are probed via legacy way, as different
machine have different interrupt arrangement, we can't cover all
of them in dt.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
v7: Drop bus-range, correct I/O ports address.
---
 arch/mips/boot/dts/loongson/rs780e-pch.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/mips/boot/dts/loongson/rs780e-pch.dtsi b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
index 8687c4f7370a..d0d5d60a8697 100644
--- a/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
+++ b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
@@ -9,6 +9,18 @@ bus@10000000 {
 				0 0x40000000 0 0x40000000 0 0x40000000
 				0xfd 0xfe000000 0xfd 0xfe000000  0 0x2000000 /* PCI Config Space */>;
 
+		pci@1a000000 {
+			compatible = "loongson,rs780e-pci";
+			device_type = "pci";
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			reg = <0 0x1a000000 0 0x02000000>;
+
+			ranges = <0x01000000 0 0x00004000 0 0x18004000 0 0x00004000>,
+				 <0x02000000 0 0x40000000 0 0x40000000 0 0x40000000>;
+		};
+
 		isa {
 			compatible = "isa";
 			#address-cells = <2>;
-- 
2.26.0.rc2


^ permalink raw reply related	[flat|nested] 63+ messages in thread

* [PATCH v7 5/5] MIPS: Loongson64: Switch to generic PCI driver
  2020-04-28  1:14 ` [PATCH v7 0/5] Loongson PCI Generic Driver Jiaxun Yang
                     ` (3 preceding siblings ...)
  2020-04-28  1:14   ` [PATCH v7 4/5] MIPS: DTS: Loongson64: Add PCI Controller Node Jiaxun Yang
@ 2020-04-28  1:14   ` Jiaxun Yang
  4 siblings, 0 replies; 63+ messages in thread
From: Jiaxun Yang @ 2020-04-28  1:14 UTC (permalink / raw)
  To: linux-mips
  Cc: Jiaxun Yang, Bjorn Helgaas, Rob Herring, Thomas Bogendoerfer,
	Huacai Chen, Lorenzo Pieralisi, Paul Burton, linux-pci,
	devicetree, linux-kernel

We can now enable generic PCI driver in Kconfig, and remove legacy
PCI driver code.

Radeon vbios quirk is moved to the platform folder to fit the
new structure.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 arch/mips/Kconfig                  |   1 +
 arch/mips/loongson64/Makefile      |   2 +-
 arch/mips/loongson64/vbios_quirk.c |  29 ++++++++
 arch/mips/pci/Makefile             |   1 -
 arch/mips/pci/fixup-loongson3.c    |  71 ------------------
 arch/mips/pci/ops-loongson3.c      | 116 -----------------------------
 6 files changed, 31 insertions(+), 189 deletions(-)
 create mode 100644 arch/mips/loongson64/vbios_quirk.c
 delete mode 100644 arch/mips/pci/fixup-loongson3.c
 delete mode 100644 arch/mips/pci/ops-loongson3.c

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 0519ca9f00f9..7a4fcc4ade1f 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -480,6 +480,7 @@ config MACH_LOONGSON64
 	select IRQ_MIPS_CPU
 	select NR_CPUS_DEFAULT_64
 	select USE_GENERIC_EARLY_PRINTK_8250
+	select PCI_DRIVERS_GENERIC
 	select SYS_HAS_CPU_LOONGSON64
 	select SYS_HAS_EARLY_PRINTK
 	select SYS_SUPPORTS_SMP
diff --git a/arch/mips/loongson64/Makefile b/arch/mips/loongson64/Makefile
index 6f3c2b47f66f..6f81b822aeae 100644
--- a/arch/mips/loongson64/Makefile
+++ b/arch/mips/loongson64/Makefile
@@ -8,5 +8,5 @@ obj-$(CONFIG_MACH_LOONGSON64) += cop2-ex.o platform.o dma.o \
 obj-$(CONFIG_SMP)	+= smp.o
 obj-$(CONFIG_NUMA)	+= numa.o
 obj-$(CONFIG_RS780_HPET) += hpet.o
-obj-$(CONFIG_PCI) += pci.o
 obj-$(CONFIG_SUSPEND) += pm.o
+obj-$(CONFIG_PCI_QUIRKS) += vbios_quirk.o
diff --git a/arch/mips/loongson64/vbios_quirk.c b/arch/mips/loongson64/vbios_quirk.c
new file mode 100644
index 000000000000..1f0a462aeddd
--- /dev/null
+++ b/arch/mips/loongson64/vbios_quirk.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <linux/pci.h>
+#include <loongson.h>
+
+static void pci_fixup_radeon(struct pci_dev *pdev)
+{
+	struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
+
+	if (res->start)
+		return;
+
+	if (!loongson_sysconf.vgabios_addr)
+		return;
+
+	pci_disable_rom(pdev);
+	if (res->parent)
+		release_resource(res);
+
+	res->start = virt_to_phys((void *) loongson_sysconf.vgabios_addr);
+	res->end   = res->start + 256*1024 - 1;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ROM_SHADOW |
+		     IORESOURCE_PCI_FIXED;
+
+	dev_info(&pdev->dev, "BAR %d: assigned %pR for Radeon ROM\n",
+		 PCI_ROM_RESOURCE, res);
+}
+DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, 0x9615,
+				PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_radeon);
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 342ce10ef593..438f10955d89 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -35,7 +35,6 @@ obj-$(CONFIG_LASAT)		+= pci-lasat.o
 obj-$(CONFIG_MIPS_COBALT)	+= fixup-cobalt.o
 obj-$(CONFIG_LEMOTE_FULOONG2E)	+= fixup-fuloong2e.o ops-loongson2.o
 obj-$(CONFIG_LEMOTE_MACH2F)	+= fixup-lemote2f.o ops-loongson2.o
-obj-$(CONFIG_MACH_LOONGSON64)	+= fixup-loongson3.o ops-loongson3.o
 obj-$(CONFIG_MIPS_MALTA)	+= fixup-malta.o pci-malta.o
 obj-$(CONFIG_PMC_MSP7120_GW)	+= fixup-pmcmsp.o ops-pmcmsp.o
 obj-$(CONFIG_PMC_MSP7120_EVAL)	+= fixup-pmcmsp.o ops-pmcmsp.o
diff --git a/arch/mips/pci/fixup-loongson3.c b/arch/mips/pci/fixup-loongson3.c
deleted file mode 100644
index 8a741c2c6685..000000000000
--- a/arch/mips/pci/fixup-loongson3.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * fixup-loongson3.c
- *
- * Copyright (C) 2012 Lemote, Inc.
- * Author: Xiang Yu, xiangy@lemote.com
- *         Chen Huacai, chenhc@lemote.com
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- * THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- * WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- * NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- * USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-
-#include <linux/pci.h>
-#include <boot_param.h>
-
-static void print_fixup_info(const struct pci_dev *pdev)
-{
-	dev_info(&pdev->dev, "Device %x:%x, irq %d\n",
-			pdev->vendor, pdev->device, pdev->irq);
-}
-
-int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
-	print_fixup_info(dev);
-	return dev->irq;
-}
-
-static void pci_fixup_radeon(struct pci_dev *pdev)
-{
-	struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
-
-	if (res->start)
-		return;
-
-	if (!loongson_sysconf.vgabios_addr)
-		return;
-
-	pci_disable_rom(pdev);
-	if (res->parent)
-		release_resource(res);
-
-	res->start = virt_to_phys((void *) loongson_sysconf.vgabios_addr);
-	res->end   = res->start + 256*1024 - 1;
-	res->flags = IORESOURCE_MEM | IORESOURCE_ROM_SHADOW |
-		     IORESOURCE_PCI_FIXED;
-
-	dev_info(&pdev->dev, "BAR %d: assigned %pR for Radeon ROM\n",
-		 PCI_ROM_RESOURCE, res);
-}
-
-DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
-				PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_radeon);
-
-/* Do platform specific device initialization at pci_enable_device() time */
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
-	return 0;
-}
diff --git a/arch/mips/pci/ops-loongson3.c b/arch/mips/pci/ops-loongson3.c
deleted file mode 100644
index 2f6ad36bdea6..000000000000
--- a/arch/mips/pci/ops-loongson3.c
+++ /dev/null
@@ -1,116 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-
-#include <asm/mips-boards/bonito64.h>
-
-#include <loongson.h>
-
-#define PCI_ACCESS_READ  0
-#define PCI_ACCESS_WRITE 1
-
-#define HT1LO_PCICFG_BASE      0x1a000000
-#define HT1LO_PCICFG_BASE_TP1  0x1b000000
-
-static int loongson3_pci_config_access(unsigned char access_type,
-		struct pci_bus *bus, unsigned int devfn,
-		int where, u32 *data)
-{
-	unsigned char busnum = bus->number;
-	int function = PCI_FUNC(devfn);
-	int device = PCI_SLOT(devfn);
-	int reg = where & ~3;
-	void *addrp;
-	u64 addr;
-
-	if (where < PCI_CFG_SPACE_SIZE) { /* standard config */
-		addr = (busnum << 16) | (device << 11) | (function << 8) | reg;
-		if (busnum == 0) {
-			if (device > 31)
-				return PCIBIOS_DEVICE_NOT_FOUND;
-			addrp = (void *)TO_UNCAC(HT1LO_PCICFG_BASE | addr);
-		} else {
-			addrp = (void *)TO_UNCAC(HT1LO_PCICFG_BASE_TP1 | addr);
-		}
-	} else if (where < PCI_CFG_SPACE_EXP_SIZE) {  /* extended config */
-		struct pci_dev *rootdev;
-
-		rootdev = pci_get_domain_bus_and_slot(0, 0, 0);
-		if (!rootdev)
-			return PCIBIOS_DEVICE_NOT_FOUND;
-
-		addr = pci_resource_start(rootdev, 3);
-		if (!addr)
-			return PCIBIOS_DEVICE_NOT_FOUND;
-
-		addr |= busnum << 20 | device << 15 | function << 12 | reg;
-		addrp = (void *)TO_UNCAC(addr);
-	} else {
-		return PCIBIOS_DEVICE_NOT_FOUND;
-	}
-
-	if (access_type == PCI_ACCESS_WRITE)
-		writel(*data, addrp);
-	else {
-		*data = readl(addrp);
-		if (*data == 0xffffffff) {
-			*data = -1;
-			return PCIBIOS_DEVICE_NOT_FOUND;
-		}
-	}
-	return PCIBIOS_SUCCESSFUL;
-}
-
-static int loongson3_pci_pcibios_read(struct pci_bus *bus, unsigned int devfn,
-				 int where, int size, u32 *val)
-{
-	u32 data = 0;
-	int ret = loongson3_pci_config_access(PCI_ACCESS_READ,
-			bus, devfn, where, &data);
-
-	if (ret != PCIBIOS_SUCCESSFUL)
-		return ret;
-
-	if (size == 1)
-		*val = (data >> ((where & 3) << 3)) & 0xff;
-	else if (size == 2)
-		*val = (data >> ((where & 3) << 3)) & 0xffff;
-	else
-		*val = data;
-
-	return PCIBIOS_SUCCESSFUL;
-}
-
-static int loongson3_pci_pcibios_write(struct pci_bus *bus, unsigned int devfn,
-				  int where, int size, u32 val)
-{
-	u32 data = 0;
-	int ret;
-
-	if (size == 4)
-		data = val;
-	else {
-		ret = loongson3_pci_config_access(PCI_ACCESS_READ,
-				bus, devfn, where, &data);
-		if (ret != PCIBIOS_SUCCESSFUL)
-			return ret;
-
-		if (size == 1)
-			data = (data & ~(0xff << ((where & 3) << 3))) |
-			    (val << ((where & 3) << 3));
-		else if (size == 2)
-			data = (data & ~(0xffff << ((where & 3) << 3))) |
-			    (val << ((where & 3) << 3));
-	}
-
-	ret = loongson3_pci_config_access(PCI_ACCESS_WRITE,
-			bus, devfn, where, &data);
-
-	return ret;
-}
-
-struct pci_ops loongson_pci_ops = {
-	.read = loongson3_pci_pcibios_read,
-	.write = loongson3_pci_pcibios_write
-};
-- 
2.26.0.rc2


^ permalink raw reply related	[flat|nested] 63+ messages in thread

* Re: [PATCH v7 2/5] PCI: Add Loongson PCI Controller support
  2020-04-28  1:14   ` [PATCH v7 2/5] PCI: Add Loongson PCI Controller support Jiaxun Yang
@ 2020-04-29 18:43     ` Rob Herring
  2020-05-04 23:43     ` Bjorn Helgaas
  1 sibling, 0 replies; 63+ messages in thread
From: Rob Herring @ 2020-04-29 18:43 UTC (permalink / raw)
  To: Jiaxun Yang
  Cc: linux-mips, Bjorn Helgaas, Thomas Bogendoerfer, Huacai Chen,
	Lorenzo Pieralisi, Paul Burton, linux-pci, devicetree,
	linux-kernel

On Tue, Apr 28, 2020 at 09:14:17AM +0800, Jiaxun Yang wrote:
> This controller can be found on Loongson-2K SoC, Loongson-3
> systems with RS780E/LS7A PCH.
> 
> The RS780E part of code was previously located at
> arch/mips/pci/ops-loongson3.c and now it can use generic PCI
> driver implementation.
> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> 
> --
> v2:
> 	- Clean up according to rob's suggestions
> 	- Claim that it can't work as a module
> v3:
> 	- Fix a typo
> v4:
> 	- More clean-ups: Drop flag check, use devfn
> v7:
> 	- Fix ordering according to huacai's suggestion
> ---
>  drivers/pci/controller/Kconfig        |  10 +
>  drivers/pci/controller/Makefile       |   1 +
>  drivers/pci/controller/pci-loongson.c | 251 ++++++++++++++++++++++++++
>  3 files changed, 262 insertions(+)
>  create mode 100644 drivers/pci/controller/pci-loongson.c

Reviewed-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 63+ messages in thread

* Re: [PATCH v7 2/5] PCI: Add Loongson PCI Controller support
  2020-04-28  1:14   ` [PATCH v7 2/5] PCI: Add Loongson PCI Controller support Jiaxun Yang
  2020-04-29 18:43     ` Rob Herring
@ 2020-05-04 23:43     ` Bjorn Helgaas
  2020-05-06  6:08       ` Jiaxun Yang
  1 sibling, 1 reply; 63+ messages in thread
From: Bjorn Helgaas @ 2020-05-04 23:43 UTC (permalink / raw)
  To: Jiaxun Yang
  Cc: linux-mips, Bjorn Helgaas, Rob Herring, Thomas Bogendoerfer,
	Huacai Chen, Lorenzo Pieralisi, Paul Burton, linux-pci,
	devicetree, linux-kernel

On Tue, Apr 28, 2020 at 09:14:17AM +0800, Jiaxun Yang wrote:
> This controller can be found on Loongson-2K SoC, Loongson-3
> systems with RS780E/LS7A PCH.
> 
> The RS780E part of code was previously located at
> arch/mips/pci/ops-loongson3.c and now it can use generic PCI
> driver implementation.
> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> 
> --
> v2:
> 	- Clean up according to rob's suggestions
> 	- Claim that it can't work as a module
> v3:
> 	- Fix a typo
> v4:
> 	- More clean-ups: Drop flag check, use devfn
> v7:
> 	- Fix ordering according to huacai's suggestion
> ---
>  drivers/pci/controller/Kconfig        |  10 +
>  drivers/pci/controller/Makefile       |   1 +
>  drivers/pci/controller/pci-loongson.c | 251 ++++++++++++++++++++++++++
>  3 files changed, 262 insertions(+)
>  create mode 100644 drivers/pci/controller/pci-loongson.c
> 
> diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> index 91bfdb784829..ae36edb1d7db 100644
> --- a/drivers/pci/controller/Kconfig
> +++ b/drivers/pci/controller/Kconfig
> @@ -258,6 +258,16 @@ config PCI_HYPERV_INTERFACE
>  	  The Hyper-V PCI Interface is a helper driver allows other drivers to
>  	  have a common interface with the Hyper-V PCI frontend driver.
>  
> +config PCI_LOONGSON
> +	bool "LOONGSON PCI Controller"
> +	depends on MACH_LOONGSON64 || COMPILE_TEST
> +	depends on OF
> +	depends on PCI_QUIRKS
> +	default MACH_LOONGSON64
> +	help
> +	  Say Y here if you want to enable PCI controller support on
> +	  Loongson systems.
> +
>  source "drivers/pci/controller/dwc/Kconfig"
>  source "drivers/pci/controller/mobiveil/Kconfig"
>  source "drivers/pci/controller/cadence/Kconfig"
> diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
> index 158c59771824..fbac4b0190a0 100644
> --- a/drivers/pci/controller/Makefile
> +++ b/drivers/pci/controller/Makefile
> @@ -28,6 +28,7 @@ obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
>  obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
>  obj-$(CONFIG_VMD) += vmd.o
>  obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
> +obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o

This is apparently a PCIe controller, not a Conventional PCI
controller, since you reference PCIe-specific things like MRRS below.

If that's the case, I'd name it pcie-loongson.c.

>  # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
>  obj-y				+= dwc/
>  obj-y				+= mobiveil/
> diff --git a/drivers/pci/controller/pci-loongson.c b/drivers/pci/controller/pci-loongson.c
> new file mode 100644
> index 000000000000..db1ebf42faf3
> --- /dev/null
> +++ b/drivers/pci/controller/pci-loongson.c
> @@ -0,0 +1,251 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Loongson PCI Host Controller Driver
> + *
> + * Copyright (C) 2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
> + */
> +
> +#include <linux/of_device.h>
> +#include <linux/of_pci.h>
> +#include <linux/pci.h>
> +#include <linux/pci_ids.h>
> +
> +#include "../pci.h"
> +
> +/* Device IDs */
> +#define DEV_PCIE_PORT_0	0x7a09
> +#define DEV_PCIE_PORT_1	0x7a19
> +#define DEV_PCIE_PORT_2	0x7a29
> +
> +#define DEV_LS2K_APB	0x7a02
> +#define DEV_LS7A_CONF	0x7a10
> +#define DEV_LS7A_LPC	0x7a0c
> +
> +#define FLAG_CFG0	BIT(0)
> +#define FLAG_CFG1	BIT(1)
> +#define FLAG_DEV_FIX	BIT(2)
> +
> +struct loongson_pci {
> +	void __iomem *cfg0_base;
> +	void __iomem *cfg1_base;
> +	struct platform_device *pdev;
> +	u32 flags;
> +};
> +
> +/* Fixup wrong class code in PCIe bridges */
> +static void bridge_class_quirk(struct pci_dev *dev)
> +{
> +	dev->class = PCI_CLASS_BRIDGE_PCI << 8;
> +}
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON,
> +			DEV_PCIE_PORT_0, bridge_class_quirk);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON,
> +			DEV_PCIE_PORT_1, bridge_class_quirk);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON,
> +			DEV_PCIE_PORT_2, bridge_class_quirk);
> +
> +static void system_bus_quirk(struct pci_dev *pdev)
> +{
> +	u16 tmp;
> +
> +	pdev->mmio_always_on = 1;
> +	pdev->non_compliant_bars = 1;
> +	/* Enable MEM & IO Decoding */
> +	pci_read_config_word(pdev, PCI_STATUS, &tmp);
> +	tmp |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
> +	pci_write_config_word(pdev, PCI_STATUS, tmp);

This needs some sort of explanation.  Is the non_compliant_bars part
an erratum?

And why can't we disable MEM/IO decoding?

You're also writing PCI_COMMAND_* bits to the PCI_STATUS register,
which is clearly broken.

Since we need an update for at least the PCI_STATUS part, there's
a little minor bike-shedding below.

> +}
> +
> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
> +			DEV_LS2K_APB, system_bus_quirk);
> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
> +			DEV_LS7A_CONF, system_bus_quirk);
> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
> +			DEV_LS7A_LPC, system_bus_quirk);
> +
> +static void loongson_mrrs_quirk(struct pci_dev *dev)
> +{
> +	struct pci_bus *bus = dev->bus;
> +	struct pci_dev *bridge;
> +	static const struct pci_device_id bridge_devids[] = {
> +		{ PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_0) },
> +		{ PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_1) },
> +		{ PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_2) },
> +		{ 0, },
> +	};
> +
> +
> +	/* look for the matching bridge */
> +	while (!pci_is_root_bus(bus)) {
> +		bridge = bus->self;
> +		bus = bus->parent;
> +		/*
> +		 * Some Loongson PCIE ports has a h/w limitation of
> +		 * 256 bytes maximum read request size. It can't handle
> +		 * anything higher than this. So force this limit on
> +		 * any devices attached under these ports.

s/PCIE/PCIe/
s/ports has/ports have/
s/It can't/They can't/
s/anything higher/anything larger/

> +		 */
> +		if (pci_match_id(bridge_devids, bridge)) {
> +			if (pcie_get_readrq(dev) > 256) {
> +				dev_info(&dev->dev, "limiting MRRS to 256\n");

pci_info(dev, ...)

> +				pcie_set_readrq(dev, 256);
> +			}
> +			break;
> +		}
> +	}
> +}
> +DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, loongson_mrrs_quirk);
> +
> +static void __iomem *cfg1_map(struct loongson_pci *priv, int bus,
> +				unsigned int devfn, int where)
> +{
> +	unsigned long addroff = 0x0;
> +
> +	if (bus != 0)
> +		addroff |= BIT(28); /* Type 1 Access */
> +	addroff |= (where & 0xff) | ((where & 0xf00) << 16);
> +	addroff |= (bus << 16) | (devfn << 8);
> +	return priv->cfg1_base + addroff;
> +}
> +
> +static void __iomem *cfg0_map(struct loongson_pci *priv, int bus,
> +				unsigned int devfn, int where)
> +{
> +	unsigned long addroff = 0x0;
> +
> +	if (bus != 0)
> +		addroff |= BIT(24); /* Type 1 Access */
> +	addroff |= (bus << 16) | (devfn << 8) | where;
> +	return priv->cfg0_base + addroff;
> +}
> +
> +void __iomem *pci_loongson_map_bus(struct pci_bus *bus, unsigned int devfn,
> +			       int where)
> +{
> +	unsigned char busnum = bus->number;
> +	struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
> +	struct loongson_pci *priv =  pci_host_bridge_priv(bridge);
> +
> +	/*
> +	 * Do not read more than one device on the bus other than
> +	 * the host bridge.
> +	 */
> +	if (bus->primary != 0 && PCI_SLOT(devfn) > 0 &&
> +		priv->flags & FLAG_DEV_FIX)

IIUC, FLAG_DEV_FIX is a workaround for a hardware issue, so this would
be easier to read as:

  if (priv->flags & FLAG_DEV_FIX && bus->primary != 0 ...

> +		return NULL;
> +
> +	/* CFG0 can only access standard space */
> +	if (where < PCI_CFG_SPACE_SIZE && priv->cfg0_base)
> +		return cfg0_map(priv, busnum, devfn, where);
> +
> +	/* CFG1 can access extended space */
> +	if (where < PCI_CFG_SPACE_EXP_SIZE && priv->cfg1_base)
> +		return cfg1_map(priv, busnum, devfn, where);
> +
> +	return NULL;
> +}
> +
> +static int loongson_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
> +{
> +	int irq;
> +	u8 val;
> +
> +	irq = of_irq_parse_and_map_pci(dev, slot, pin);
> +	if (irq > 0)
> +		return irq;
> +
> +	/* Care i8259 legacy systems */
> +	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &val);
> +	/* i8259 only have 15 IRQs */
> +	if (val > 15)
> +		return 0;
> +
> +	return val;
> +}
> +
> +/* H/w only accept 32-bit PCI operations */

I'm sure you're aware that the spec actually requires 8- and 16-bit
operations, at least for config writes.  You probably see a few of the
warnings from pci_generic_config_write32()?  Just FYI for any future
hardware designs.

> +static struct pci_ops loongson_pci_ops = {
> +	.map_bus = pci_loongson_map_bus,
> +	.read	= pci_generic_config_read32,
> +	.write	= pci_generic_config_write32,
> +};
> +
> +static const struct of_device_id loongson_pci_of_match[] = {
> +	{ .compatible = "loongson,ls2k-pci",
> +		.data = (void *)(FLAG_CFG0 | FLAG_CFG1 | FLAG_DEV_FIX), },
> +	{ .compatible = "loongson,ls7a-pci",
> +		.data = (void *)(FLAG_CFG0 | FLAG_CFG1 | FLAG_DEV_FIX), },
> +	{ .compatible = "loongson,rs780e-pci",
> +		.data = (void *)(FLAG_CFG0), },
> +	{}
> +};
> +
> +static int loongson_pci_probe(struct platform_device *pdev)
> +{
> +	struct loongson_pci *priv;
> +	struct device *dev = &pdev->dev;
> +	struct device_node *node = dev->of_node;
> +	struct pci_host_bridge *bridge;
> +	struct resource *regs;
> +	int err;
> +
> +	if (!node)
> +		return -ENODEV;
> +
> +	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*priv));
> +	if (!bridge)
> +		return -ENODEV;
> +
> +	priv = pci_host_bridge_priv(bridge);
> +	priv->pdev = pdev;
> +	priv->flags = (unsigned long)of_device_get_match_data(dev);
> +
> +	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	if (!regs) {
> +		dev_err(dev, "missing mem resources for cfg0\n");
> +		return -EINVAL;
> +	}
> +
> +	priv->cfg0_base = devm_pci_remap_cfg_resource(dev, regs);
> +	if (IS_ERR(priv->cfg0_base))
> +		return PTR_ERR(priv->cfg0_base);
> +
> +	/* CFG1 is optional */
> +	if (priv->flags & FLAG_CFG1) {
> +		regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> +		if (!regs)
> +			dev_info(dev, "missing mem resource for cfg1\n");
> +		else {
> +			priv->cfg1_base = devm_pci_remap_cfg_resource(dev, regs);
> +			if (IS_ERR(priv->cfg1_base))
> +				priv->cfg1_base = NULL;
> +		}
> +	}
> +
> +	err = pci_parse_request_of_pci_ranges(dev, &bridge->windows,
> +						&bridge->dma_ranges, NULL);
> +	if (err) {
> +		dev_err(dev, "Failed to get bridge resources\n");

Some of your messages are capitalized (maybe just this one) and others
are lower-case.

> +		return err;
> +	}
> +
> +	bridge->dev.parent = dev;
> +	bridge->sysdata = priv;
> +	bridge->ops = &loongson_pci_ops;
> +	bridge->map_irq = loongson_map_irq;
> +
> +	err = pci_host_probe(bridge);
> +	if (err)
> +		return err;
> +
> +	return 0;
> +}
> +
> +static struct platform_driver loongson_pci_driver = {
> +	.driver = {
> +		.name = "loongson-pci",
> +		.of_match_table = loongson_pci_of_match,
> +	},
> +	.probe = loongson_pci_probe,
> +};
> +builtin_platform_driver(loongson_pci_driver);
> -- 
> 2.26.0.rc2
> 

^ permalink raw reply	[flat|nested] 63+ messages in thread

* Re: [PATCH v7 2/5] PCI: Add Loongson PCI Controller support
  2020-05-04 23:43     ` Bjorn Helgaas
@ 2020-05-06  6:08       ` Jiaxun Yang
  0 siblings, 0 replies; 63+ messages in thread
From: Jiaxun Yang @ 2020-05-06  6:08 UTC (permalink / raw)
  To: Bjorn Helgaas
  Cc: linux-mips, Bjorn Helgaas, Rob Herring, Thomas Bogendoerfer,
	Huacai Chen, Lorenzo Pieralisi, Paul Burton, linux-pci,
	devicetree, linux-kernel

On Mon, 4 May 2020 18:43:29 -0500
Bjorn Helgaas <helgaas@kernel.org> wrote:

> On Tue, Apr 28, 2020 at 09:14:17AM +0800, Jiaxun Yang wrote:
> > This controller can be found on Loongson-2K SoC, Loongson-3
> > systems with RS780E/LS7A PCH.
> > 
> > The RS780E part of code was previously located at
> > arch/mips/pci/ops-loongson3.c and now it can use generic PCI
> > driver implementation.
> > 
> > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> > 
> > --
> > v2:
> > 	- Clean up according to rob's suggestions
> > 	- Claim that it can't work as a module
> > v3:
> > 	- Fix a typo
> > v4:
> > 	- More clean-ups: Drop flag check, use devfn
> > v7:
> > 	- Fix ordering according to huacai's suggestion
> > ---
> >  drivers/pci/controller/Kconfig        |  10 +
> >  drivers/pci/controller/Makefile       |   1 +
> >  drivers/pci/controller/pci-loongson.c | 251
> > ++++++++++++++++++++++++++ 3 files changed, 262 insertions(+)
> >  create mode 100644 drivers/pci/controller/pci-loongson.c
> > 
> > diff --git a/drivers/pci/controller/Kconfig
> > b/drivers/pci/controller/Kconfig index 91bfdb784829..ae36edb1d7db
> > 100644 --- a/drivers/pci/controller/Kconfig
> > +++ b/drivers/pci/controller/Kconfig
> > @@ -258,6 +258,16 @@ config PCI_HYPERV_INTERFACE
> >  	  The Hyper-V PCI Interface is a helper driver allows
> > other drivers to have a common interface with the Hyper-V PCI
> > frontend driver. 
> > +config PCI_LOONGSON
> > +	bool "LOONGSON PCI Controller"
> > +	depends on MACH_LOONGSON64 || COMPILE_TEST
> > +	depends on OF
> > +	depends on PCI_QUIRKS
> > +	default MACH_LOONGSON64
> > +	help
> > +	  Say Y here if you want to enable PCI controller support
> > on
> > +	  Loongson systems.
> > +
> >  source "drivers/pci/controller/dwc/Kconfig"
> >  source "drivers/pci/controller/mobiveil/Kconfig"
> >  source "drivers/pci/controller/cadence/Kconfig"
> > diff --git a/drivers/pci/controller/Makefile
> > b/drivers/pci/controller/Makefile index 158c59771824..fbac4b0190a0
> > 100644 --- a/drivers/pci/controller/Makefile
> > +++ b/drivers/pci/controller/Makefile
> > @@ -28,6 +28,7 @@ obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
> >  obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
> >  obj-$(CONFIG_VMD) += vmd.o
> >  obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
> > +obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o  
> 
> This is apparently a PCIe controller, not a Conventional PCI
> controller, since you reference PCIe-specific things like MRRS below.
> 
> If that's the case, I'd name it pcie-loongson.c.
> 

Hi Bjorn,

Thanks for your careful review.

I'll resolve other comments, for the naming as it's exactly a PCI host
bridge with some on-chip devices like AHCI, Ethernet, VGA controller
attached on it, also some PCI to PCIe bridges are attached on it to
provide PCIe port. I'd still prefer pci-loongson as it's name.

--
Jiaxun Yang

^ permalink raw reply	[flat|nested] 63+ messages in thread

* [PATCH v8 1/5] PCI: Don't disable decoding when mmio_always_on is set
  2020-04-27  6:05 [PATCH v6 0/5] Loongson PCI Generic Driver Jiaxun Yang
                   ` (5 preceding siblings ...)
  2020-04-28  1:14 ` [PATCH v7 0/5] Loongson PCI Generic Driver Jiaxun Yang
@ 2020-05-08 11:34 ` Jiaxun Yang
  2020-05-08 11:34   ` [PATCH v8 2/5] PCI: Add Loongson PCI Controller support Jiaxun Yang
                     ` (3 more replies)
  2020-05-12  7:43 ` [PATCH v9 1/5] PCI: Don't disable decoding when mmio_always_on is set Jiaxun Yang
                   ` (2 subsequent siblings)
  9 siblings, 4 replies; 63+ messages in thread
From: Jiaxun Yang @ 2020-05-08 11:34 UTC (permalink / raw)
  To: maz
  Cc: Jiaxun Yang, Bjorn Helgaas, Rob Herring, Thomas Bogendoerfer,
	Huacai Chen, Lorenzo Pieralisi, Paul Burton, linux-pci,
	devicetree, linux-kernel, linux-mips

Don't disable MEM/IO decoding when a device have both non_compliant_bars
and mmio_always_on.

That would allow us quirk devices with junk in BARs but can't disable
their decoding.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 drivers/pci/probe.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 77b8a145c39b..d9c2c3301a8a 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -1822,7 +1822,7 @@ int pci_setup_device(struct pci_dev *dev)
 	/* Device class may be changed after fixup */
 	class = dev->class >> 8;
 
-	if (dev->non_compliant_bars) {
+	if (dev->non_compliant_bars && !dev->mmio_always_on) {
 		pci_read_config_word(dev, PCI_COMMAND, &cmd);
 		if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
 			pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
-- 
2.26.0.rc2


^ permalink raw reply related	[flat|nested] 63+ messages in thread

* [PATCH v8 2/5] PCI: Add Loongson PCI Controller support
  2020-05-08 11:34 ` [PATCH v8 1/5] PCI: Don't disable decoding when mmio_always_on is set Jiaxun Yang
@ 2020-05-08 11:34   ` Jiaxun Yang
  2020-05-08 17:17     ` Bjorn Helgaas
  2020-05-08 11:34   ` [PATCH v8 3/5] dt-bindings: Document Loongson PCI Host Controller Jiaxun Yang
                     ` (2 subsequent siblings)
  3 siblings, 1 reply; 63+ messages in thread
From: Jiaxun Yang @ 2020-05-08 11:34 UTC (permalink / raw)
  To: maz
  Cc: Jiaxun Yang, Rob Herring, Bjorn Helgaas, Rob Herring,
	Thomas Bogendoerfer, Huacai Chen, Lorenzo Pieralisi, Paul Burton,
	linux-pci, devicetree, linux-kernel, linux-mips

This controller can be found on Loongson-2K SoC, Loongson-3
systems with RS780E/LS7A PCH.

The RS780E part of code was previously located at
arch/mips/pci/ops-loongson3.c and now it can use generic PCI
driver implementation.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Rob Herring <robh@kernel.org>

--
v2:
	- Clean up according to rob's suggestions
	- Claim that it can't work as a module
v3:
	- Fix a typo
v4:
	- More clean-ups: Drop flag check, use devfn
v7:
	- Fix ordering according to huacai's suggestion
v8:
	- Style clean and bugfix according to Bjorn's review
---
 drivers/pci/controller/Kconfig        |  10 +
 drivers/pci/controller/Makefile       |   1 +
 drivers/pci/controller/pci-loongson.c | 257 ++++++++++++++++++++++++++
 3 files changed, 268 insertions(+)
 create mode 100644 drivers/pci/controller/pci-loongson.c

diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 91bfdb784829..ae36edb1d7db 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -258,6 +258,16 @@ config PCI_HYPERV_INTERFACE
 	  The Hyper-V PCI Interface is a helper driver allows other drivers to
 	  have a common interface with the Hyper-V PCI frontend driver.
 
+config PCI_LOONGSON
+	bool "LOONGSON PCI Controller"
+	depends on MACH_LOONGSON64 || COMPILE_TEST
+	depends on OF
+	depends on PCI_QUIRKS
+	default MACH_LOONGSON64
+	help
+	  Say Y here if you want to enable PCI controller support on
+	  Loongson systems.
+
 source "drivers/pci/controller/dwc/Kconfig"
 source "drivers/pci/controller/mobiveil/Kconfig"
 source "drivers/pci/controller/cadence/Kconfig"
diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
index 158c59771824..fbac4b0190a0 100644
--- a/drivers/pci/controller/Makefile
+++ b/drivers/pci/controller/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
 obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
 obj-$(CONFIG_VMD) += vmd.o
 obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
+obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o
 # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
 obj-y				+= dwc/
 obj-y				+= mobiveil/
diff --git a/drivers/pci/controller/pci-loongson.c b/drivers/pci/controller/pci-loongson.c
new file mode 100644
index 000000000000..76442f44a41e
--- /dev/null
+++ b/drivers/pci/controller/pci-loongson.c
@@ -0,0 +1,257 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Loongson PCI Host Controller Driver
+ *
+ * Copyright (C) 2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
+ */
+
+#include <linux/of_device.h>
+#include <linux/of_pci.h>
+#include <linux/pci.h>
+#include <linux/pci_ids.h>
+
+#include "../pci.h"
+
+/* Device IDs */
+#define DEV_PCIE_PORT_0	0x7a09
+#define DEV_PCIE_PORT_1	0x7a19
+#define DEV_PCIE_PORT_2	0x7a29
+
+#define DEV_LS2K_APB	0x7a02
+#define DEV_LS7A_CONF	0x7a10
+#define DEV_LS7A_LPC	0x7a0c
+
+#define FLAG_CFG0	BIT(0)
+#define FLAG_CFG1	BIT(1)
+#define FLAG_DEV_FIX	BIT(2)
+
+struct loongson_pci {
+	void __iomem *cfg0_base;
+	void __iomem *cfg1_base;
+	struct platform_device *pdev;
+	u32 flags;
+};
+
+/* Fixup wrong class code in PCIe bridges */
+static void bridge_class_quirk(struct pci_dev *dev)
+{
+	dev->class = PCI_CLASS_BRIDGE_PCI << 8;
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON,
+			DEV_PCIE_PORT_0, bridge_class_quirk);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON,
+			DEV_PCIE_PORT_1, bridge_class_quirk);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON,
+			DEV_PCIE_PORT_2, bridge_class_quirk);
+
+static void system_bus_quirk(struct pci_dev *pdev)
+{
+	u16 tmp;
+
+	/* 
+	 * System buses on Loongson system contain garbage in BARs
+	 * but their decoding need to be enabled to ensure devices
+	 * under system buses are reachable. In most cases it should
+	 * be done by the firmware.
+	 */
+	pdev->mmio_always_on = 1;
+	pdev->non_compliant_bars = 1;
+	/* Enable MEM & IO Decoding */
+	pci_read_config_word(pdev, PCI_COMMAND, &tmp);
+	tmp |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
+	pci_write_config_word(pdev, PCI_COMMAND, tmp);
+}
+
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
+			DEV_LS2K_APB, system_bus_quirk);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
+			DEV_LS7A_CONF, system_bus_quirk);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
+			DEV_LS7A_LPC, system_bus_quirk);
+
+static void loongson_mrrs_quirk(struct pci_dev *dev)
+{
+	struct pci_bus *bus = dev->bus;
+	struct pci_dev *bridge;
+	static const struct pci_device_id bridge_devids[] = {
+		{ PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_0) },
+		{ PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_1) },
+		{ PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_2) },
+		{ 0, },
+	};
+
+
+	/* look for the matching bridge */
+	while (!pci_is_root_bus(bus)) {
+		bridge = bus->self;
+		bus = bus->parent;
+		/*
+		 * Some Loongson PCIe ports have a h/w limitation of
+		 * 256 bytes maximum read request size. They can't handle
+		 * anything larger than this. So force this limit on
+		 * any devices attached under these ports.
+		 */
+		if (pci_match_id(bridge_devids, bridge)) {
+			if (pcie_get_readrq(dev) > 256) {
+				pci_info(dev, "limiting MRRS to 256\n");
+				pcie_set_readrq(dev, 256);
+			}
+			break;
+		}
+	}
+}
+DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, loongson_mrrs_quirk);
+
+static void __iomem *cfg1_map(struct loongson_pci *priv, int bus,
+				unsigned int devfn, int where)
+{
+	unsigned long addroff = 0x0;
+
+	if (bus != 0)
+		addroff |= BIT(28); /* Type 1 Access */
+	addroff |= (where & 0xff) | ((where & 0xf00) << 16);
+	addroff |= (bus << 16) | (devfn << 8);
+	return priv->cfg1_base + addroff;
+}
+
+static void __iomem *cfg0_map(struct loongson_pci *priv, int bus,
+				unsigned int devfn, int where)
+{
+	unsigned long addroff = 0x0;
+
+	if (bus != 0)
+		addroff |= BIT(24); /* Type 1 Access */
+	addroff |= (bus << 16) | (devfn << 8) | where;
+	return priv->cfg0_base + addroff;
+}
+
+void __iomem *pci_loongson_map_bus(struct pci_bus *bus, unsigned int devfn,
+			       int where)
+{
+	unsigned char busnum = bus->number;
+	struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
+	struct loongson_pci *priv =  pci_host_bridge_priv(bridge);
+
+	/*
+	 * Do not read more than one device on the bus other than
+	 * the host bridge.
+	 */
+	if (priv->flags & FLAG_DEV_FIX && bus->primary != 0 &&
+		PCI_SLOT(devfn) > 0)
+		return NULL;
+
+	/* CFG0 can only access standard space */
+	if (where < PCI_CFG_SPACE_SIZE && priv->cfg0_base)
+		return cfg0_map(priv, busnum, devfn, where);
+
+	/* CFG1 can access extended space */
+	if (where < PCI_CFG_SPACE_EXP_SIZE && priv->cfg1_base)
+		return cfg1_map(priv, busnum, devfn, where);
+
+	return NULL;
+}
+
+static int loongson_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+	int irq;
+	u8 val;
+
+	irq = of_irq_parse_and_map_pci(dev, slot, pin);
+	if (irq > 0)
+		return irq;
+
+	/* Care i8259 legacy systems */
+	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &val);
+	/* i8259 only have 15 IRQs */
+	if (val > 15)
+		return 0;
+
+	return val;
+}
+
+/* H/w only accept 32-bit PCI operations */
+static struct pci_ops loongson_pci_ops = {
+	.map_bus = pci_loongson_map_bus,
+	.read	= pci_generic_config_read32,
+	.write	= pci_generic_config_write32,
+};
+
+static const struct of_device_id loongson_pci_of_match[] = {
+	{ .compatible = "loongson,ls2k-pci",
+		.data = (void *)(FLAG_CFG0 | FLAG_CFG1 | FLAG_DEV_FIX), },
+	{ .compatible = "loongson,ls7a-pci",
+		.data = (void *)(FLAG_CFG0 | FLAG_CFG1 | FLAG_DEV_FIX), },
+	{ .compatible = "loongson,rs780e-pci",
+		.data = (void *)(FLAG_CFG0), },
+	{}
+};
+
+static int loongson_pci_probe(struct platform_device *pdev)
+{
+	struct loongson_pci *priv;
+	struct device *dev = &pdev->dev;
+	struct device_node *node = dev->of_node;
+	struct pci_host_bridge *bridge;
+	struct resource *regs;
+	int err;
+
+	if (!node)
+		return -ENODEV;
+
+	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*priv));
+	if (!bridge)
+		return -ENODEV;
+
+	priv = pci_host_bridge_priv(bridge);
+	priv->pdev = pdev;
+	priv->flags = (unsigned long)of_device_get_match_data(dev);
+
+	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!regs) {
+		dev_err(dev, "missing mem resources for cfg0\n");
+		return -EINVAL;
+	}
+
+	priv->cfg0_base = devm_pci_remap_cfg_resource(dev, regs);
+	if (IS_ERR(priv->cfg0_base))
+		return PTR_ERR(priv->cfg0_base);
+
+	/* CFG1 is optional */
+	if (priv->flags & FLAG_CFG1) {
+		regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+		if (!regs)
+			dev_info(dev, "missing mem resource for cfg1\n");
+		else {
+			priv->cfg1_base = devm_pci_remap_cfg_resource(dev, regs);
+			if (IS_ERR(priv->cfg1_base))
+				priv->cfg1_base = NULL;
+		}
+	}
+
+	err = pci_parse_request_of_pci_ranges(dev, &bridge->windows,
+						&bridge->dma_ranges, NULL);
+	if (err) {
+		dev_err(dev, "failed to get bridge resources\n");
+		return err;
+	}
+
+	bridge->dev.parent = dev;
+	bridge->sysdata = priv;
+	bridge->ops = &loongson_pci_ops;
+	bridge->map_irq = loongson_map_irq;
+
+	err = pci_host_probe(bridge);
+	if (err)
+		return err;
+
+	return 0;
+}
+
+static struct platform_driver loongson_pci_driver = {
+	.driver = {
+		.name = "loongson-pci",
+		.of_match_table = loongson_pci_of_match,
+	},
+	.probe = loongson_pci_probe,
+};
+builtin_platform_driver(loongson_pci_driver);
-- 
2.26.0.rc2


^ permalink raw reply related	[flat|nested] 63+ messages in thread

* [PATCH v8 3/5] dt-bindings: Document Loongson PCI Host Controller
  2020-05-08 11:34 ` [PATCH v8 1/5] PCI: Don't disable decoding when mmio_always_on is set Jiaxun Yang
  2020-05-08 11:34   ` [PATCH v8 2/5] PCI: Add Loongson PCI Controller support Jiaxun Yang
@ 2020-05-08 11:34   ` Jiaxun Yang
  2020-05-08 11:34   ` [PATCH v8 4/5] MIPS: DTS: Loongson64: Add PCI Controller Node Jiaxun Yang
  2020-05-08 11:34   ` [PATCH v8 5/5] MIPS: Loongson64: Switch to generic PCI driver Jiaxun Yang
  3 siblings, 0 replies; 63+ messages in thread
From: Jiaxun Yang @ 2020-05-08 11:34 UTC (permalink / raw)
  To: maz
  Cc: Jiaxun Yang, Rob Herring, Bjorn Helgaas, Rob Herring,
	Thomas Bogendoerfer, Huacai Chen, Lorenzo Pieralisi, Paul Burton,
	linux-pci, devicetree, linux-kernel, linux-mips

PCI host controller found on Loongson PCHs and SoCs.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../devicetree/bindings/pci/loongson.yaml     | 62 +++++++++++++++++++
 1 file changed, 62 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/loongson.yaml

diff --git a/Documentation/devicetree/bindings/pci/loongson.yaml b/Documentation/devicetree/bindings/pci/loongson.yaml
new file mode 100644
index 000000000000..30e7cf1aeb87
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/loongson.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/loongson.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Loongson PCI Host Controller
+
+maintainers:
+  - Jiaxun Yang <jiaxun.yang@flygoat.com>
+
+description: |+
+  PCI host controller found on Loongson PCHs and SoCs.
+
+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+  compatible:
+    oneOf:
+      - const: loongson,ls2k-pci
+      - const: loongson,ls7a-pci
+      - const: loongson,rs780e-pci
+
+  reg:
+    minItems: 1
+    maxItems: 2
+    items:
+      - description: CFG0 standard config space register
+      - description: CFG1 extended config space register
+
+  ranges:
+    minItems: 1
+    maxItems: 3
+
+
+required:
+  - compatible
+  - reg
+  - ranges
+
+examples:
+  - |
+
+    bus {
+        #address-cells = <2>;
+        #size-cells = <2>;
+        pcie@1a000000 {
+            compatible = "loongson,rs780e-pci";
+            device_type = "pci";
+            #address-cells = <3>;
+            #size-cells = <2>;
+
+            // CPU_PHYSICAL(2)  SIZE(2)
+            reg = <0x0 0x1a000000  0x0 0x2000000>;
+
+            // BUS_ADDRESS(3)  CPU_PHYSICAL(2)  SIZE(2)
+            ranges = <0x01000000 0x0 0x00004000  0x0 0x00004000  0x0 0x00004000>,
+                     <0x02000000 0x0 0x40000000  0x0 0x40000000  0x0 0x40000000>;
+        };
+    };
+...
-- 
2.26.0.rc2


^ permalink raw reply related	[flat|nested] 63+ messages in thread

* [PATCH v8 4/5] MIPS: DTS: Loongson64: Add PCI Controller Node
  2020-05-08 11:34 ` [PATCH v8 1/5] PCI: Don't disable decoding when mmio_always_on is set Jiaxun Yang
  2020-05-08 11:34   ` [PATCH v8 2/5] PCI: Add Loongson PCI Controller support Jiaxun Yang
  2020-05-08 11:34   ` [PATCH v8 3/5] dt-bindings: Document Loongson PCI Host Controller Jiaxun Yang
@ 2020-05-08 11:34   ` Jiaxun Yang
  2020-05-08 11:34   ` [PATCH v8 5/5] MIPS: Loongson64: Switch to generic PCI driver Jiaxun Yang
  3 siblings, 0 replies; 63+ messages in thread
From: Jiaxun Yang @ 2020-05-08 11:34 UTC (permalink / raw)
  To: maz
  Cc: Jiaxun Yang, Bjorn Helgaas, Rob Herring, Thomas Bogendoerfer,
	Huacai Chen, Lorenzo Pieralisi, Paul Burton, linux-pci,
	devicetree, linux-kernel, linux-mips

Add PCI Host controller node for Loongson64 with RS780E PCH dts.
Note that PCI interrupts are probed via legacy way, as different
machine have different interrupt arrangement, we can't cover all
of them in dt.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 arch/mips/boot/dts/loongson/rs780e-pch.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/mips/boot/dts/loongson/rs780e-pch.dtsi b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
index 8687c4f7370a..d0d5d60a8697 100644
--- a/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
+++ b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
@@ -9,6 +9,18 @@ bus@10000000 {
 				0 0x40000000 0 0x40000000 0 0x40000000
 				0xfd 0xfe000000 0xfd 0xfe000000  0 0x2000000 /* PCI Config Space */>;
 
+		pci@1a000000 {
+			compatible = "loongson,rs780e-pci";
+			device_type = "pci";
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			reg = <0 0x1a000000 0 0x02000000>;
+
+			ranges = <0x01000000 0 0x00004000 0 0x18004000 0 0x00004000>,
+				 <0x02000000 0 0x40000000 0 0x40000000 0 0x40000000>;
+		};
+
 		isa {
 			compatible = "isa";
 			#address-cells = <2>;
-- 
2.26.0.rc2


^ permalink raw reply related	[flat|nested] 63+ messages in thread

* [PATCH v8 5/5] MIPS: Loongson64: Switch to generic PCI driver
  2020-05-08 11:34 ` [PATCH v8 1/5] PCI: Don't disable decoding when mmio_always_on is set Jiaxun Yang
                     ` (2 preceding siblings ...)
  2020-05-08 11:34   ` [PATCH v8 4/5] MIPS: DTS: Loongson64: Add PCI Controller Node Jiaxun Yang
@ 2020-05-08 11:34   ` Jiaxun Yang
  2020-05-08 22:04     ` Bjorn Helgaas
  3 siblings, 1 reply; 63+ messages in thread
From: Jiaxun Yang @ 2020-05-08 11:34 UTC (permalink / raw)
  To: maz
  Cc: Jiaxun Yang, Bjorn Helgaas, Rob Herring, Thomas Bogendoerfer,
	Huacai Chen, Lorenzo Pieralisi, Paul Burton, linux-pci,
	devicetree, linux-kernel, linux-mips

We can now enable generic PCI driver in Kconfig, and remove legacy
PCI driver code.

Radeon vbios quirk is moved to the platform folder to fit the
new structure.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 arch/mips/Kconfig                  |   1 +
 arch/mips/loongson64/Makefile      |   2 +-
 arch/mips/loongson64/vbios_quirk.c |  29 ++++++++
 arch/mips/pci/Makefile             |   1 -
 arch/mips/pci/fixup-loongson3.c    |  71 ------------------
 arch/mips/pci/ops-loongson3.c      | 116 -----------------------------
 6 files changed, 31 insertions(+), 189 deletions(-)
 create mode 100644 arch/mips/loongson64/vbios_quirk.c
 delete mode 100644 arch/mips/pci/fixup-loongson3.c
 delete mode 100644 arch/mips/pci/ops-loongson3.c

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 0519ca9f00f9..7a4fcc4ade1f 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -480,6 +480,7 @@ config MACH_LOONGSON64
 	select IRQ_MIPS_CPU
 	select NR_CPUS_DEFAULT_64
 	select USE_GENERIC_EARLY_PRINTK_8250
+	select PCI_DRIVERS_GENERIC
 	select SYS_HAS_CPU_LOONGSON64
 	select SYS_HAS_EARLY_PRINTK
 	select SYS_SUPPORTS_SMP
diff --git a/arch/mips/loongson64/Makefile b/arch/mips/loongson64/Makefile
index 6f3c2b47f66f..6f81b822aeae 100644
--- a/arch/mips/loongson64/Makefile
+++ b/arch/mips/loongson64/Makefile
@@ -8,5 +8,5 @@ obj-$(CONFIG_MACH_LOONGSON64) += cop2-ex.o platform.o dma.o \
 obj-$(CONFIG_SMP)	+= smp.o
 obj-$(CONFIG_NUMA)	+= numa.o
 obj-$(CONFIG_RS780_HPET) += hpet.o
-obj-$(CONFIG_PCI) += pci.o
 obj-$(CONFIG_SUSPEND) += pm.o
+obj-$(CONFIG_PCI_QUIRKS) += vbios_quirk.o
diff --git a/arch/mips/loongson64/vbios_quirk.c b/arch/mips/loongson64/vbios_quirk.c
new file mode 100644
index 000000000000..1f0a462aeddd
--- /dev/null
+++ b/arch/mips/loongson64/vbios_quirk.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <linux/pci.h>
+#include <loongson.h>
+
+static void pci_fixup_radeon(struct pci_dev *pdev)
+{
+	struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
+
+	if (res->start)
+		return;
+
+	if (!loongson_sysconf.vgabios_addr)
+		return;
+
+	pci_disable_rom(pdev);
+	if (res->parent)
+		release_resource(res);
+
+	res->start = virt_to_phys((void *) loongson_sysconf.vgabios_addr);
+	res->end   = res->start + 256*1024 - 1;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ROM_SHADOW |
+		     IORESOURCE_PCI_FIXED;
+
+	dev_info(&pdev->dev, "BAR %d: assigned %pR for Radeon ROM\n",
+		 PCI_ROM_RESOURCE, res);
+}
+DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, 0x9615,
+				PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_radeon);
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 342ce10ef593..438f10955d89 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -35,7 +35,6 @@ obj-$(CONFIG_LASAT)		+= pci-lasat.o
 obj-$(CONFIG_MIPS_COBALT)	+= fixup-cobalt.o
 obj-$(CONFIG_LEMOTE_FULOONG2E)	+= fixup-fuloong2e.o ops-loongson2.o
 obj-$(CONFIG_LEMOTE_MACH2F)	+= fixup-lemote2f.o ops-loongson2.o
-obj-$(CONFIG_MACH_LOONGSON64)	+= fixup-loongson3.o ops-loongson3.o
 obj-$(CONFIG_MIPS_MALTA)	+= fixup-malta.o pci-malta.o
 obj-$(CONFIG_PMC_MSP7120_GW)	+= fixup-pmcmsp.o ops-pmcmsp.o
 obj-$(CONFIG_PMC_MSP7120_EVAL)	+= fixup-pmcmsp.o ops-pmcmsp.o
diff --git a/arch/mips/pci/fixup-loongson3.c b/arch/mips/pci/fixup-loongson3.c
deleted file mode 100644
index 8a741c2c6685..000000000000
--- a/arch/mips/pci/fixup-loongson3.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * fixup-loongson3.c
- *
- * Copyright (C) 2012 Lemote, Inc.
- * Author: Xiang Yu, xiangy@lemote.com
- *         Chen Huacai, chenhc@lemote.com
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- * THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- * WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- * NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- * USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-
-#include <linux/pci.h>
-#include <boot_param.h>
-
-static void print_fixup_info(const struct pci_dev *pdev)
-{
-	dev_info(&pdev->dev, "Device %x:%x, irq %d\n",
-			pdev->vendor, pdev->device, pdev->irq);
-}
-
-int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
-	print_fixup_info(dev);
-	return dev->irq;
-}
-
-static void pci_fixup_radeon(struct pci_dev *pdev)
-{
-	struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
-
-	if (res->start)
-		return;
-
-	if (!loongson_sysconf.vgabios_addr)
-		return;
-
-	pci_disable_rom(pdev);
-	if (res->parent)
-		release_resource(res);
-
-	res->start = virt_to_phys((void *) loongson_sysconf.vgabios_addr);
-	res->end   = res->start + 256*1024 - 1;
-	res->flags = IORESOURCE_MEM | IORESOURCE_ROM_SHADOW |
-		     IORESOURCE_PCI_FIXED;
-
-	dev_info(&pdev->dev, "BAR %d: assigned %pR for Radeon ROM\n",
-		 PCI_ROM_RESOURCE, res);
-}
-
-DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
-				PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_radeon);
-
-/* Do platform specific device initialization at pci_enable_device() time */
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
-	return 0;
-}
diff --git a/arch/mips/pci/ops-loongson3.c b/arch/mips/pci/ops-loongson3.c
deleted file mode 100644
index 2f6ad36bdea6..000000000000
--- a/arch/mips/pci/ops-loongson3.c
+++ /dev/null
@@ -1,116 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-
-#include <asm/mips-boards/bonito64.h>
-
-#include <loongson.h>
-
-#define PCI_ACCESS_READ  0
-#define PCI_ACCESS_WRITE 1
-
-#define HT1LO_PCICFG_BASE      0x1a000000
-#define HT1LO_PCICFG_BASE_TP1  0x1b000000
-
-static int loongson3_pci_config_access(unsigned char access_type,
-		struct pci_bus *bus, unsigned int devfn,
-		int where, u32 *data)
-{
-	unsigned char busnum = bus->number;
-	int function = PCI_FUNC(devfn);
-	int device = PCI_SLOT(devfn);
-	int reg = where & ~3;
-	void *addrp;
-	u64 addr;
-
-	if (where < PCI_CFG_SPACE_SIZE) { /* standard config */
-		addr = (busnum << 16) | (device << 11) | (function << 8) | reg;
-		if (busnum == 0) {
-			if (device > 31)
-				return PCIBIOS_DEVICE_NOT_FOUND;
-			addrp = (void *)TO_UNCAC(HT1LO_PCICFG_BASE | addr);
-		} else {
-			addrp = (void *)TO_UNCAC(HT1LO_PCICFG_BASE_TP1 | addr);
-		}
-	} else if (where < PCI_CFG_SPACE_EXP_SIZE) {  /* extended config */
-		struct pci_dev *rootdev;
-
-		rootdev = pci_get_domain_bus_and_slot(0, 0, 0);
-		if (!rootdev)
-			return PCIBIOS_DEVICE_NOT_FOUND;
-
-		addr = pci_resource_start(rootdev, 3);
-		if (!addr)
-			return PCIBIOS_DEVICE_NOT_FOUND;
-
-		addr |= busnum << 20 | device << 15 | function << 12 | reg;
-		addrp = (void *)TO_UNCAC(addr);
-	} else {
-		return PCIBIOS_DEVICE_NOT_FOUND;
-	}
-
-	if (access_type == PCI_ACCESS_WRITE)
-		writel(*data, addrp);
-	else {
-		*data = readl(addrp);
-		if (*data == 0xffffffff) {
-			*data = -1;
-			return PCIBIOS_DEVICE_NOT_FOUND;
-		}
-	}
-	return PCIBIOS_SUCCESSFUL;
-}
-
-static int loongson3_pci_pcibios_read(struct pci_bus *bus, unsigned int devfn,
-				 int where, int size, u32 *val)
-{
-	u32 data = 0;
-	int ret = loongson3_pci_config_access(PCI_ACCESS_READ,
-			bus, devfn, where, &data);
-
-	if (ret != PCIBIOS_SUCCESSFUL)
-		return ret;
-
-	if (size == 1)
-		*val = (data >> ((where & 3) << 3)) & 0xff;
-	else if (size == 2)
-		*val = (data >> ((where & 3) << 3)) & 0xffff;
-	else
-		*val = data;
-
-	return PCIBIOS_SUCCESSFUL;
-}
-
-static int loongson3_pci_pcibios_write(struct pci_bus *bus, unsigned int devfn,
-				  int where, int size, u32 val)
-{
-	u32 data = 0;
-	int ret;
-
-	if (size == 4)
-		data = val;
-	else {
-		ret = loongson3_pci_config_access(PCI_ACCESS_READ,
-				bus, devfn, where, &data);
-		if (ret != PCIBIOS_SUCCESSFUL)
-			return ret;
-
-		if (size == 1)
-			data = (data & ~(0xff << ((where & 3) << 3))) |
-			    (val << ((where & 3) << 3));
-		else if (size == 2)
-			data = (data & ~(0xffff << ((where & 3) << 3))) |
-			    (val << ((where & 3) << 3));
-	}
-
-	ret = loongson3_pci_config_access(PCI_ACCESS_WRITE,
-			bus, devfn, where, &data);
-
-	return ret;
-}
-
-struct pci_ops loongson_pci_ops = {
-	.read = loongson3_pci_pcibios_read,
-	.write = loongson3_pci_pcibios_write
-};
-- 
2.26.0.rc2


^ permalink raw reply related	[flat|nested] 63+ messages in thread

* Re: [PATCH v8 2/5] PCI: Add Loongson PCI Controller support
  2020-05-08 11:34   ` [PATCH v8 2/5] PCI: Add Loongson PCI Controller support Jiaxun Yang
@ 2020-05-08 17:17     ` Bjorn Helgaas
  2020-05-08 17:28       ` Jiaxun Yang
  0 siblings, 1 reply; 63+ messages in thread
From: Bjorn Helgaas @ 2020-05-08 17:17 UTC (permalink / raw)
  To: Jiaxun Yang
  Cc: maz, Rob Herring, Bjorn Helgaas, Rob Herring,
	Thomas Bogendoerfer, Huacai Chen, Lorenzo Pieralisi, Paul Burton,
	linux-pci, devicetree, linux-kernel, linux-mips

On Fri, May 08, 2020 at 07:34:02PM +0800, Jiaxun Yang wrote:
> This controller can be found on Loongson-2K SoC, Loongson-3
> systems with RS780E/LS7A PCH.
> 
> The RS780E part of code was previously located at
> arch/mips/pci/ops-loongson3.c and now it can use generic PCI
> driver implementation.
> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Reviewed-by: Rob Herring <robh@kernel.org>

> +static void system_bus_quirk(struct pci_dev *pdev)
> +{
> +	u16 tmp;
> +
> +	/* 
> +	 * System buses on Loongson system contain garbage in BARs
> +	 * but their decoding need to be enabled to ensure devices
> +	 * under system buses are reachable. In most cases it should
> +	 * be done by the firmware.

This isn't a very satisfying explanation because devices that have
decoding enabled can interfere with other devices in the system, and I
can't tell whether that's a problem here.

What happens when you turn on MEM/IO decoding below?  Does the device
decode any address space?  How do we know what it is?  Is it related
to the BAR contents?

I'm a little dubious about the need for the PCI_COMMAND write because
the previous version didn't do it (since it incorrectly wrote to
PCI_STATUS), and I assume that version worked.

> +	pdev->mmio_always_on = 1;
> +	pdev->non_compliant_bars = 1;
> +	/* Enable MEM & IO Decoding */
> +	pci_read_config_word(pdev, PCI_COMMAND, &tmp);
> +	tmp |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
> +	pci_write_config_word(pdev, PCI_COMMAND, tmp);


> +}
> +

Omit this blank line.

> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
> +			DEV_LS2K_APB, system_bus_quirk);
> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
> +			DEV_LS7A_CONF, system_bus_quirk);
> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
> +			DEV_LS7A_LPC, system_bus_quirk);
> +
> +static void loongson_mrrs_quirk(struct pci_dev *dev)
> +{
> +	struct pci_bus *bus = dev->bus;
> +	struct pci_dev *bridge;
> +	static const struct pci_device_id bridge_devids[] = {
> +		{ PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_0) },
> +		{ PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_1) },
> +		{ PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_2) },
> +		{ 0, },
> +	};
> +
> +

Remove one of these blank lines.

> +	/* look for the matching bridge */
> +	while (!pci_is_root_bus(bus)) {
> +		bridge = bus->self;
> +		bus = bus->parent;
> +		/*
> +		 * Some Loongson PCIe ports have a h/w limitation of
> +		 * 256 bytes maximum read request size. They can't handle
> +		 * anything larger than this. So force this limit on
> +		 * any devices attached under these ports.
> +		 */
> +		if (pci_match_id(bridge_devids, bridge)) {
> +			if (pcie_get_readrq(dev) > 256) {
> +				pci_info(dev, "limiting MRRS to 256\n");
> +				pcie_set_readrq(dev, 256);
> +			}
> +			break;
> +		}
> +	}
> +}
> +DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, loongson_mrrs_quirk);

> +void __iomem *pci_loongson_map_bus(struct pci_bus *bus, unsigned int devfn,
> +			       int where)
> +{
> +	unsigned char busnum = bus->number;
> +	struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
> +	struct loongson_pci *priv =  pci_host_bridge_priv(bridge);
> +
> +	/*
> +	 * Do not read more than one device on the bus other than
> +	 * the host bridge.

s/host bridge/root bus/ ?

IIUC, the test below assumes the root bus is bus 0, which is not
necessarily the case.  Many other .*_map_bus() implementations have
similar tests for devices on the root bus:

  al_pcie_map_bus(...)
  {
    if (bus->number == cfg->busr.start) {

> +	if (priv->flags & FLAG_DEV_FIX && bus->primary != 0 &&
> +		PCI_SLOT(devfn) > 0)
> +		return NULL;

^ permalink raw reply	[flat|nested] 63+ messages in thread

* Re: [PATCH v8 2/5] PCI: Add Loongson PCI Controller support
  2020-05-08 17:17     ` Bjorn Helgaas
@ 2020-05-08 17:28       ` Jiaxun Yang
  2020-05-08 19:34         ` Bjorn Helgaas
  0 siblings, 1 reply; 63+ messages in thread
From: Jiaxun Yang @ 2020-05-08 17:28 UTC (permalink / raw)
  To: Bjorn Helgaas
  Cc: maz, Rob Herring, Bjorn Helgaas, Rob Herring,
	Thomas Bogendoerfer, Huacai Chen, Lorenzo Pieralisi, Paul Burton,
	linux-pci, devicetree, linux-kernel, linux-mips



于 2020年5月9日 GMT+08:00 上午1:17:30, Bjorn Helgaas <helgaas@kernel.org> 写到:
>On Fri, May 08, 2020 at 07:34:02PM +0800, Jiaxun Yang wrote:
>> This controller can be found on Loongson-2K SoC, Loongson-3
>> systems with RS780E/LS7A PCH.
>> 
>> The RS780E part of code was previously located at
>> arch/mips/pci/ops-loongson3.c and now it can use generic PCI
>> driver implementation.
>> 
>> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>> Reviewed-by: Rob Herring <robh@kernel.org>
>
>> +static void system_bus_quirk(struct pci_dev *pdev)
>> +{
>> +	u16 tmp;
>> +
>> +	/* 
>> +	 * System buses on Loongson system contain garbage in BARs
>> +	 * but their decoding need to be enabled to ensure devices
>> +	 * under system buses are reachable. In most cases it should
>> +	 * be done by the firmware.
>
>This isn't a very satisfying explanation because devices that have
>decoding enabled can interfere with other devices in the system, and I
>can't tell whether that's a problem here.
>
>What happens when you turn on MEM/IO decoding below?  Does the device
>decode any address space?  How do we know what it is?  Is it related
>to the BAR contents?
>
>I'm a little dubious about the need for the PCI_COMMAND write because
>the previous version didn't do it (since it incorrectly wrote to
>PCI_STATUS), and I assume that version worked.

Hi,
Sorry, but that's all I can tell from the chips manual as I'm not a employee
of the vendor.

My assumption is these BAR contains the address of those system components
that already configured by firmware and we shouldn't touch it.

In fact according to my tests if we let Kernel probe these BAR then the
system will hang immediately.

Chip manual suggested OS to ensure decoding is enabled
so I'm doing like this. But without this system can also work.

Do you think I should drop it until figure out what was it actually doing?

>
>> +	pdev->mmio_always_on = 1;
>> +	pdev->non_compliant_bars = 1;
>> +	/* Enable MEM & IO Decoding */
>> +	pci_read_config_word(pdev, PCI_COMMAND, &tmp);
>> +	tmp |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
>> +	pci_write_config_word(pdev, PCI_COMMAND, tmp);
>
>
>> +}
>> +
>
>Omit this blank line.

Ack

>
>> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
>> +			DEV_LS2K_APB, system_bus_quirk);
>> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
>> +			DEV_LS7A_CONF, system_bus_quirk);
>> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
>> +			DEV_LS7A_LPC, system_bus_quirk);
>> +
>> +static void loongson_mrrs_quirk(struct pci_dev *dev)
>> +{
>> +	struct pci_bus *bus = dev->bus;
>> +	struct pci_dev *bridge;
>> +	static const struct pci_device_id bridge_devids[] = {
>> +		{ PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_0) },
>> +		{ PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_1) },
>> +		{ PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_2) },
>> +		{ 0, },
>> +	};
>> +
>> +
>
>Remove one of these blank lines.

Ack

>
>> +	/* look for the matching bridge */
>> +	while (!pci_is_root_bus(bus)) {
>> +		bridge = bus->self;
>> +		bus = bus->parent;
>> +		/*
>> +		 * Some Loongson PCIe ports have a h/w limitation of
>> +		 * 256 bytes maximum read request size. They can't handle
>> +		 * anything larger than this. So force this limit on
>> +		 * any devices attached under these ports.
>> +		 */
>> +		if (pci_match_id(bridge_devids, bridge)) {
>> +			if (pcie_get_readrq(dev) > 256) {
>> +				pci_info(dev, "limiting MRRS to 256\n");
>> +				pcie_set_readrq(dev, 256);
>> +			}
>> +			break;
>> +		}
>> +	}
>> +}
>> +DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, loongson_mrrs_quirk);
>
>> +void __iomem *pci_loongson_map_bus(struct pci_bus *bus, unsigned int devfn,
>> +			       int where)
>> +{
>> +	unsigned char busnum = bus->number;
>> +	struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
>> +	struct loongson_pci *priv =  pci_host_bridge_priv(bridge);
>> +
>> +	/*
>> +	 * Do not read more than one device on the bus other than
>> +	 * the host bridge.
>
>s/host bridge/root bus/ ?
>
>IIUC, the test below assumes the root bus is bus 0, which is not
>necessarily the case.  Many other .*_map_bus() implementations have
>similar tests for devices on the root bus:

Ack

>
>  al_pcie_map_bus(...)
>  {
>    if (bus->number == cfg->busr.start) {
>
>> +	if (priv->flags & FLAG_DEV_FIX && bus->primary != 0 &&
>> +		PCI_SLOT(devfn) > 0)
>> +		return NULL;

Thanks!

-- 
Jiaxun Yang

^ permalink raw reply	[flat|nested] 63+ messages in thread

* Re: [PATCH v7 1/5] PCI: Don't disable decoding when mmio_always_on is set
  2020-04-28  1:14   ` [PATCH v7 1/5] PCI: Don't disable decoding when mmio_always_on is set Jiaxun Yang
@ 2020-05-08 18:51     ` Bjorn Helgaas
  2020-05-20 20:55     ` Rob Herring
  1 sibling, 0 replies; 63+ messages in thread
From: Bjorn Helgaas @ 2020-05-08 18:51 UTC (permalink / raw)
  To: Jiaxun Yang
  Cc: linux-mips, Bjorn Helgaas, Rob Herring, Thomas Bogendoerfer,
	Huacai Chen, Lorenzo Pieralisi, Paul Burton, linux-pci,
	devicetree, linux-kernel

On Tue, Apr 28, 2020 at 09:14:16AM +0800, Jiaxun Yang wrote:
> Don't disable MEM/IO decoding when a device have both non_compliant_bars
> and mmio_always_on.
> 
> That would allow us quirk devices with junk in BARs but can't disable
> their decoding.
> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>

Acked-by: Bjorn Helgaas <bhelgaas@google.com>

> ---
>  drivers/pci/probe.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> index 77b8a145c39b..d9c2c3301a8a 100644
> --- a/drivers/pci/probe.c
> +++ b/drivers/pci/probe.c
> @@ -1822,7 +1822,7 @@ int pci_setup_device(struct pci_dev *dev)
>  	/* Device class may be changed after fixup */
>  	class = dev->class >> 8;
>  
> -	if (dev->non_compliant_bars) {
> +	if (dev->non_compliant_bars && !dev->mmio_always_on) {
>  		pci_read_config_word(dev, PCI_COMMAND, &cmd);
>  		if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
>  			pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
> -- 
> 2.26.0.rc2
> 

^ permalink raw reply	[flat|nested] 63+ messages in thread

* Re: [PATCH v8 2/5] PCI: Add Loongson PCI Controller support
  2020-05-08 17:28       ` Jiaxun Yang
@ 2020-05-08 19:34         ` Bjorn Helgaas
  0 siblings, 0 replies; 63+ messages in thread
From: Bjorn Helgaas @ 2020-05-08 19:34 UTC (permalink / raw)
  To: Jiaxun Yang
  Cc: maz, Rob Herring, Bjorn Helgaas, Rob Herring,
	Thomas Bogendoerfer, Huacai Chen, Lorenzo Pieralisi, Paul Burton,
	linux-pci, devicetree, linux-kernel, linux-mips

On Sat, May 09, 2020 at 01:28:24AM +0800, Jiaxun Yang wrote:
> 于 2020年5月9日 GMT+08:00 上午1:17:30, Bjorn Helgaas <helgaas@kernel.org> 写到:
> >On Fri, May 08, 2020 at 07:34:02PM +0800, Jiaxun Yang wrote:
> >> This controller can be found on Loongson-2K SoC, Loongson-3
> >> systems with RS780E/LS7A PCH.
> >> 
> >> The RS780E part of code was previously located at
> >> arch/mips/pci/ops-loongson3.c and now it can use generic PCI
> >> driver implementation.
> >> 
> >> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> >> Reviewed-by: Rob Herring <robh@kernel.org>
> >
> >> +static void system_bus_quirk(struct pci_dev *pdev)
> >> +{
> >> +	u16 tmp;
> >> +
> >> +	/* 
> >> +	 * System buses on Loongson system contain garbage in BARs
> >> +	 * but their decoding need to be enabled to ensure devices
> >> +	 * under system buses are reachable. In most cases it should
> >> +	 * be done by the firmware.
> >
> >This isn't a very satisfying explanation because devices that have
> >decoding enabled can interfere with other devices in the system, and I
> >can't tell whether that's a problem here.
> >
> >What happens when you turn on MEM/IO decoding below?  Does the device
> >decode any address space?  How do we know what it is?  Is it related
> >to the BAR contents?
> >
> >I'm a little dubious about the need for the PCI_COMMAND write because
> >the previous version didn't do it (since it incorrectly wrote to
> >PCI_STATUS), and I assume that version worked.
> 
> Sorry, but that's all I can tell from the chips manual as I'm not a
> employee of the vendor.
> 
> My assumption is these BAR contains the address of those system
> components that already configured by firmware and we shouldn't
> touch it.

What are the values in the BARs?  Do they look like addresses?  Would
they make sense in the iomem_resource, i.e., in /proc/iomem?

If the BARs contain addresses of devices, the kernel needs to avoid
that address space when allocating space for other devices.  But
without probing the BARs, the kernel has no idea what the *size* of
the regions is.  Does the manual say anything about that?

Can you tell if there's anything at all Linux could do with these
devices?  If they don't have BARs and they don't document any
device-specific registers in config space, there's not much value in
treating them like PCI devices at all.

I wonder if we should just make a way to completely ignore them, e.g.,
a way for pci_setup_device() to return an error.   I guess we *could*
do that already by making your early fixup set dev->hdr_type to 0xff
or something.

> In fact according to my tests if we let Kernel probe these BAR then
> the system will hang immediately.
> 
> Chip manual suggested OS to ensure decoding is enabled so I'm doing
> like this. But without this system can also work.
> 
> Do you think I should drop it until figure out what was it actually
> doing?


^ permalink raw reply	[flat|nested] 63+ messages in thread

* Re: [PATCH v8 5/5] MIPS: Loongson64: Switch to generic PCI driver
  2020-05-08 11:34   ` [PATCH v8 5/5] MIPS: Loongson64: Switch to generic PCI driver Jiaxun Yang
@ 2020-05-08 22:04     ` Bjorn Helgaas
  0 siblings, 0 replies; 63+ messages in thread
From: Bjorn Helgaas @ 2020-05-08 22:04 UTC (permalink / raw)
  To: Jiaxun Yang
  Cc: maz, Bjorn Helgaas, Rob Herring, Thomas Bogendoerfer,
	Huacai Chen, Lorenzo Pieralisi, Paul Burton, linux-pci,
	devicetree, linux-kernel, linux-mips

On Fri, May 08, 2020 at 07:34:05PM +0800, Jiaxun Yang wrote:
> We can now enable generic PCI driver in Kconfig, and remove legacy
> PCI driver code.
> 
> Radeon vbios quirk is moved to the platform folder to fit the
> new structure.

> diff --git a/arch/mips/loongson64/vbios_quirk.c b/arch/mips/loongson64/vbios_quirk.c
> new file mode 100644
> index 000000000000..1f0a462aeddd
> --- /dev/null
> +++ b/arch/mips/loongson64/vbios_quirk.c
> @@ -0,0 +1,29 @@
> +// SPDX-License-Identifier: GPL-2.0

In arch/mips/pci/fixup-loongson3.c, pci_fixup_radeon() was under "GPL
version 2 or (at your option) any later version."

Documentation/process/license-rules.rst says that corresponds to
GPL-2.0+, not GPL-2.0.

> +static void pci_fixup_radeon(struct pci_dev *pdev)
> +{
> ...
> +}

> diff --git a/arch/mips/pci/fixup-loongson3.c b/arch/mips/pci/fixup-loongson3.c
> deleted file mode 100644
> index 8a741c2c6685..000000000000
> --- a/arch/mips/pci/fixup-loongson3.c
> +++ /dev/null
> @@ -1,71 +0,0 @@
> -/*
> - * fixup-loongson3.c
> - *
> - * Copyright (C) 2012 Lemote, Inc.
> - * Author: Xiang Yu, xiangy@lemote.com
> - *         Chen Huacai, chenhc@lemote.com
> - *
> - * This program is free software; you can redistribute  it and/or modify it
> - * under  the terms of  the GNU General  Public License as published by the
> - * Free Software Foundation;  either version 2 of the  License, or (at your
> - * option) any later version.
> - *
> - * THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
> - * WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
> - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
> - * NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
> - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
> - * NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
> - * USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
> - * ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
> - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
> - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> - *
> - */
> -
> -#include <linux/pci.h>
> -#include <boot_param.h>
> -
> -static void print_fixup_info(const struct pci_dev *pdev)
> -{
> -	dev_info(&pdev->dev, "Device %x:%x, irq %d\n",
> -			pdev->vendor, pdev->device, pdev->irq);
> -}
> -
> -int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
> -{
> -	print_fixup_info(dev);
> -	return dev->irq;
> -}
> -
> -static void pci_fixup_radeon(struct pci_dev *pdev)
> -{
> -	struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
> -
> -	if (res->start)
> -		return;
> -
> -	if (!loongson_sysconf.vgabios_addr)
> -		return;
> -
> -	pci_disable_rom(pdev);
> -	if (res->parent)
> -		release_resource(res);
> -
> -	res->start = virt_to_phys((void *) loongson_sysconf.vgabios_addr);
> -	res->end   = res->start + 256*1024 - 1;
> -	res->flags = IORESOURCE_MEM | IORESOURCE_ROM_SHADOW |
> -		     IORESOURCE_PCI_FIXED;
> -
> -	dev_info(&pdev->dev, "BAR %d: assigned %pR for Radeon ROM\n",
> -		 PCI_ROM_RESOURCE, res);
> -}
> -
> -DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
> -				PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_radeon);
> -
> -/* Do platform specific device initialization at pci_enable_device() time */
> -int pcibios_plat_dev_init(struct pci_dev *dev)
> -{
> -	return 0;
> -}

^ permalink raw reply	[flat|nested] 63+ messages in thread

* [PATCH v9 1/5] PCI: Don't disable decoding when mmio_always_on is set
  2020-04-27  6:05 [PATCH v6 0/5] Loongson PCI Generic Driver Jiaxun Yang
                   ` (6 preceding siblings ...)
  2020-05-08 11:34 ` [PATCH v8 1/5] PCI: Don't disable decoding when mmio_always_on is set Jiaxun Yang
@ 2020-05-12  7:43 ` Jiaxun Yang
  2020-05-12  7:43   ` [PATCH v9 2/5] PCI: Add Loongson PCI Controller support Jiaxun Yang
                     ` (3 more replies)
  2020-05-14 13:16 ` [PATCH v10 1/5] PCI: Don't disable decoding when mmio_always_on is set Jiaxun Yang
  2020-05-26  9:21 ` [PATCH v11 0/5] Loongson Generic PCI v11 Jiaxun Yang
  9 siblings, 4 replies; 63+ messages in thread
From: Jiaxun Yang @ 2020-05-12  7:43 UTC (permalink / raw)
  To: linux-pci
  Cc: Jiaxun Yang, Bjorn Helgaas, Bjorn Helgaas, Rob Herring,
	Thomas Bogendoerfer, Huacai Chen, Lorenzo Pieralisi, Paul Burton,
	devicetree, linux-kernel, linux-mips

Don't disable MEM/IO decoding when a device have both non_compliant_bars
and mmio_always_on.

That would allow us quirk devices with junk in BARs but can't disable
their decoding.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Acked-by: Bjorn Helgaas <helgaas@kernel.org>
---
 drivers/pci/probe.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 77b8a145c39b..d9c2c3301a8a 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -1822,7 +1822,7 @@ int pci_setup_device(struct pci_dev *dev)
 	/* Device class may be changed after fixup */
 	class = dev->class >> 8;
 
-	if (dev->non_compliant_bars) {
+	if (dev->non_compliant_bars && !dev->mmio_always_on) {
 		pci_read_config_word(dev, PCI_COMMAND, &cmd);
 		if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
 			pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
-- 
2.26.2


^ permalink raw reply related	[flat|nested] 63+ messages in thread

* [PATCH v9 2/5] PCI: Add Loongson PCI Controller support
  2020-05-12  7:43 ` [PATCH v9 1/5] PCI: Don't disable decoding when mmio_always_on is set Jiaxun Yang
@ 2020-05-12  7:43   ` Jiaxun Yang
  2020-05-12 18:06     ` Bjorn Helgaas
  2020-05-12  7:43   ` [PATCH v9 3/5] dt-bindings: Document Loongson PCI Host Controller Jiaxun Yang
                     ` (2 subsequent siblings)
  3 siblings, 1 reply; 63+ messages in thread
From: Jiaxun Yang @ 2020-05-12  7:43 UTC (permalink / raw)
  To: linux-pci
  Cc: Jiaxun Yang, Rob Herring, Bjorn Helgaas, Rob Herring,
	Thomas Bogendoerfer, Huacai Chen, Lorenzo Pieralisi, Paul Burton,
	devicetree, linux-kernel, linux-mips

This controller can be found on Loongson-2K SoC, Loongson-3
systems with RS780E/LS7A PCH.

The RS780E part of code was previously located at
arch/mips/pci/ops-loongson3.c and now it can use generic PCI
driver implementation.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Rob Herring <robh@kernel.org>

--
v2:
	- Clean up according to rob's suggestions
	- Claim that it can't work as a module
v3:
	- Fix a typo
v4:
	- More clean-ups: Drop flag check, use devfn
v7:
	- Fix ordering according to huacai's suggestion
v8:
	- Style clean and bugfix according to Bjorn's review
v9:
	- Confirm with vendor about the details on system_bus BARs
	- Further cleanups
	- I think assume root_bus as 0 simplify our code a lot, as that's
		always valid to the hardware, as we're not ecam or dwc, we can't
		easily get host bus_nr via cfg, adding that will cause unnecessary
		overhead.
---
 drivers/pci/controller/Kconfig        |  10 +
 drivers/pci/controller/Makefile       |   1 +
 drivers/pci/controller/pci-loongson.c | 251 ++++++++++++++++++++++++++
 3 files changed, 262 insertions(+)
 create mode 100644 drivers/pci/controller/pci-loongson.c

diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 91bfdb784829..ae36edb1d7db 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -258,6 +258,16 @@ config PCI_HYPERV_INTERFACE
 	  The Hyper-V PCI Interface is a helper driver allows other drivers to
 	  have a common interface with the Hyper-V PCI frontend driver.
 
+config PCI_LOONGSON
+	bool "LOONGSON PCI Controller"
+	depends on MACH_LOONGSON64 || COMPILE_TEST
+	depends on OF
+	depends on PCI_QUIRKS
+	default MACH_LOONGSON64
+	help
+	  Say Y here if you want to enable PCI controller support on
+	  Loongson systems.
+
 source "drivers/pci/controller/dwc/Kconfig"
 source "drivers/pci/controller/mobiveil/Kconfig"
 source "drivers/pci/controller/cadence/Kconfig"
diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
index 158c59771824..fbac4b0190a0 100644
--- a/drivers/pci/controller/Makefile
+++ b/drivers/pci/controller/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
 obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
 obj-$(CONFIG_VMD) += vmd.o
 obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
+obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o
 # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
 obj-y				+= dwc/
 obj-y				+= mobiveil/
diff --git a/drivers/pci/controller/pci-loongson.c b/drivers/pci/controller/pci-loongson.c
new file mode 100644
index 000000000000..7673e85f9200
--- /dev/null
+++ b/drivers/pci/controller/pci-loongson.c
@@ -0,0 +1,251 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Loongson PCI Host Controller Driver
+ *
+ * Copyright (C) 2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
+ */
+
+#include <linux/of_device.h>
+#include <linux/of_pci.h>
+#include <linux/pci.h>
+#include <linux/pci_ids.h>
+
+#include "../pci.h"
+
+/* Device IDs */
+#define DEV_PCIE_PORT_0	0x7a09
+#define DEV_PCIE_PORT_1	0x7a19
+#define DEV_PCIE_PORT_2	0x7a29
+
+#define DEV_LS2K_APB	0x7a02
+#define DEV_LS7A_CONF	0x7a10
+#define DEV_LS7A_LPC	0x7a0c
+
+#define FLAG_CFG0	BIT(0)
+#define FLAG_CFG1	BIT(1)
+#define FLAG_DEV_FIX	BIT(2)
+
+struct loongson_pci {
+	void __iomem *cfg0_base;
+	void __iomem *cfg1_base;
+	struct platform_device *pdev;
+	u32 flags;
+};
+
+/* Fixup wrong class code in PCIe bridges */
+static void bridge_class_quirk(struct pci_dev *dev)
+{
+	dev->class = PCI_CLASS_BRIDGE_PCI << 8;
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON,
+			DEV_PCIE_PORT_0, bridge_class_quirk);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON,
+			DEV_PCIE_PORT_1, bridge_class_quirk);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON,
+			DEV_PCIE_PORT_2, bridge_class_quirk);
+
+static void system_bus_quirk(struct pci_dev *pdev)
+{
+	u16 tmp;
+
+	/* 
+	 * These devices are not sharing resouces with rest of devices
+	 * on host bus and firmware will ensure their BARs are placed
+	 * in safe ranges. Also there might be some config registers
+	 * in their config space so kernel shouldn't ignore them.
+	 */
+	pdev->mmio_always_on = 1;
+	pdev->non_compliant_bars = 1;
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
+			DEV_LS2K_APB, system_bus_quirk);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
+			DEV_LS7A_CONF, system_bus_quirk);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
+			DEV_LS7A_LPC, system_bus_quirk);
+
+static void loongson_mrrs_quirk(struct pci_dev *dev)
+{
+	struct pci_bus *bus = dev->bus;
+	struct pci_dev *bridge;
+	static const struct pci_device_id bridge_devids[] = {
+		{ PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_0) },
+		{ PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_1) },
+		{ PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_2) },
+		{ 0, },
+	};
+
+	/* look for the matching bridge */
+	while (!pci_is_root_bus(bus)) {
+		bridge = bus->self;
+		bus = bus->parent;
+		/*
+		 * Some Loongson PCIe ports have a h/w limitation of
+		 * 256 bytes maximum read request size. They can't handle
+		 * anything larger than this. So force this limit on
+		 * any devices attached under these ports.
+		 */
+		if (pci_match_id(bridge_devids, bridge)) {
+			if (pcie_get_readrq(dev) > 256) {
+				pci_info(dev, "limiting MRRS to 256\n");
+				pcie_set_readrq(dev, 256);
+			}
+			break;
+		}
+	}
+}
+DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, loongson_mrrs_quirk);
+
+static void __iomem *cfg1_map(struct loongson_pci *priv, int bus,
+				unsigned int devfn, int where)
+{
+	unsigned long addroff = 0x0;
+
+	if (bus != 0)
+		addroff |= BIT(28); /* Type 1 Access */
+	addroff |= (where & 0xff) | ((where & 0xf00) << 16);
+	addroff |= (bus << 16) | (devfn << 8);
+	return priv->cfg1_base + addroff;
+}
+
+static void __iomem *cfg0_map(struct loongson_pci *priv, int bus,
+				unsigned int devfn, int where)
+{
+	unsigned long addroff = 0x0;
+
+	if (bus != 0)
+		addroff |= BIT(24); /* Type 1 Access */
+	addroff |= (bus << 16) | (devfn << 8) | where;
+	return priv->cfg0_base + addroff;
+}
+
+void __iomem *pci_loongson_map_bus(struct pci_bus *bus, unsigned int devfn,
+			       int where)
+{
+	unsigned char busnum = bus->number;
+	struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
+	struct loongson_pci *priv =  pci_host_bridge_priv(bridge);
+
+	/*
+	 * Do not read more than one device on the bus other than
+	 * the host bus 0.
+	 */
+	if (priv->flags & FLAG_DEV_FIX && busnum != 0 &&
+		PCI_SLOT(devfn) > 0)
+		return NULL;
+
+	/* CFG0 can only access standard space */
+	if (where < PCI_CFG_SPACE_SIZE && priv->cfg0_base)
+		return cfg0_map(priv, busnum, devfn, where);
+
+	/* CFG1 can access extended space */
+	if (where < PCI_CFG_SPACE_EXP_SIZE && priv->cfg1_base)
+		return cfg1_map(priv, busnum, devfn, where);
+
+	return NULL;
+}
+
+static int loongson_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+	int irq;
+	u8 val;
+
+	irq = of_irq_parse_and_map_pci(dev, slot, pin);
+	if (irq > 0)
+		return irq;
+
+	/* Care i8259 legacy systems */
+	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &val);
+	/* i8259 only have 15 IRQs */
+	if (val > 15)
+		return 0;
+
+	return val;
+}
+
+/* H/w only accept 32-bit PCI operations */
+static struct pci_ops loongson_pci_ops = {
+	.map_bus = pci_loongson_map_bus,
+	.read	= pci_generic_config_read32,
+	.write	= pci_generic_config_write32,
+};
+
+static const struct of_device_id loongson_pci_of_match[] = {
+	{ .compatible = "loongson,ls2k-pci",
+		.data = (void *)(FLAG_CFG0 | FLAG_CFG1 | FLAG_DEV_FIX), },
+	{ .compatible = "loongson,ls7a-pci",
+		.data = (void *)(FLAG_CFG0 | FLAG_CFG1 | FLAG_DEV_FIX), },
+	{ .compatible = "loongson,rs780e-pci",
+		.data = (void *)(FLAG_CFG0), },
+	{}
+};
+
+static int loongson_pci_probe(struct platform_device *pdev)
+{
+	struct loongson_pci *priv;
+	struct device *dev = &pdev->dev;
+	struct device_node *node = dev->of_node;
+	struct pci_host_bridge *bridge;
+	struct resource *regs;
+	int err;
+
+	if (!node)
+		return -ENODEV;
+
+	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*priv));
+	if (!bridge)
+		return -ENODEV;
+
+	priv = pci_host_bridge_priv(bridge);
+	priv->pdev = pdev;
+	priv->flags = (unsigned long)of_device_get_match_data(dev);
+
+	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!regs) {
+		dev_err(dev, "missing mem resources for cfg0\n");
+		return -EINVAL;
+	}
+
+	priv->cfg0_base = devm_pci_remap_cfg_resource(dev, regs);
+	if (IS_ERR(priv->cfg0_base))
+		return PTR_ERR(priv->cfg0_base);
+
+	/* CFG1 is optional */
+	if (priv->flags & FLAG_CFG1) {
+		regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+		if (!regs)
+			dev_info(dev, "missing mem resource for cfg1\n");
+		else {
+			priv->cfg1_base = devm_pci_remap_cfg_resource(dev, regs);
+			if (IS_ERR(priv->cfg1_base))
+				priv->cfg1_base = NULL;
+		}
+	}
+
+	err = pci_parse_request_of_pci_ranges(dev, &bridge->windows,
+						&bridge->dma_ranges, NULL);
+	if (err) {
+		dev_err(dev, "failed to get bridge resources\n");
+		return err;
+	}
+
+	bridge->dev.parent = dev;
+	bridge->sysdata = priv;
+	bridge->ops = &loongson_pci_ops;
+	bridge->map_irq = loongson_map_irq;
+
+	err = pci_host_probe(bridge);
+	if (err)
+		return err;
+
+	return 0;
+}
+
+static struct platform_driver loongson_pci_driver = {
+	.driver = {
+		.name = "loongson-pci",
+		.of_match_table = loongson_pci_of_match,
+	},
+	.probe = loongson_pci_probe,
+};
+builtin_platform_driver(loongson_pci_driver);
-- 
2.26.2


^ permalink raw reply related	[flat|nested] 63+ messages in thread

* [PATCH v9 3/5] dt-bindings: Document Loongson PCI Host Controller
  2020-05-12  7:43 ` [PATCH v9 1/5] PCI: Don't disable decoding when mmio_always_on is set Jiaxun Yang
  2020-05-12  7:43   ` [PATCH v9 2/5] PCI: Add Loongson PCI Controller support Jiaxun Yang
@ 2020-05-12  7:43   ` Jiaxun Yang
  2020-05-12  7:43   ` [PATCH v9 4/5] MIPS: DTS: Loongson64: Add PCI Controller Node Jiaxun Yang
  2020-05-12  7:43   ` [PATCH v9 5/5] MIPS: Loongson64: Switch to generic PCI driver Jiaxun Yang
  3 siblings, 0 replies; 63+ messages in thread
From: Jiaxun Yang @ 2020-05-12  7:43 UTC (permalink / raw)
  To: linux-pci
  Cc: Jiaxun Yang, Rob Herring, Bjorn Helgaas, Rob Herring,
	Thomas Bogendoerfer, Huacai Chen, Lorenzo Pieralisi, Paul Burton,
	devicetree, linux-kernel, linux-mips

PCI host controller found on Loongson PCHs and SoCs.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../devicetree/bindings/pci/loongson.yaml     | 62 +++++++++++++++++++
 1 file changed, 62 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/loongson.yaml

diff --git a/Documentation/devicetree/bindings/pci/loongson.yaml b/Documentation/devicetree/bindings/pci/loongson.yaml
new file mode 100644
index 000000000000..30e7cf1aeb87
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/loongson.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/loongson.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Loongson PCI Host Controller
+
+maintainers:
+  - Jiaxun Yang <jiaxun.yang@flygoat.com>
+
+description: |+
+  PCI host controller found on Loongson PCHs and SoCs.
+
+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+  compatible:
+    oneOf:
+      - const: loongson,ls2k-pci
+      - const: loongson,ls7a-pci
+      - const: loongson,rs780e-pci
+
+  reg:
+    minItems: 1
+    maxItems: 2
+    items:
+      - description: CFG0 standard config space register
+      - description: CFG1 extended config space register
+
+  ranges:
+    minItems: 1
+    maxItems: 3
+
+
+required:
+  - compatible
+  - reg
+  - ranges
+
+examples:
+  - |
+
+    bus {
+        #address-cells = <2>;
+        #size-cells = <2>;
+        pcie@1a000000 {
+            compatible = "loongson,rs780e-pci";
+            device_type = "pci";
+            #address-cells = <3>;
+            #size-cells = <2>;
+
+            // CPU_PHYSICAL(2)  SIZE(2)
+            reg = <0x0 0x1a000000  0x0 0x2000000>;
+
+            // BUS_ADDRESS(3)  CPU_PHYSICAL(2)  SIZE(2)
+            ranges = <0x01000000 0x0 0x00004000  0x0 0x00004000  0x0 0x00004000>,
+                     <0x02000000 0x0 0x40000000  0x0 0x40000000  0x0 0x40000000>;
+        };
+    };
+...
-- 
2.26.2


^ permalink raw reply related	[flat|nested] 63+ messages in thread

* [PATCH v9 4/5] MIPS: DTS: Loongson64: Add PCI Controller Node
  2020-05-12  7:43 ` [PATCH v9 1/5] PCI: Don't disable decoding when mmio_always_on is set Jiaxun Yang
  2020-05-12  7:43   ` [PATCH v9 2/5] PCI: Add Loongson PCI Controller support Jiaxun Yang
  2020-05-12  7:43   ` [PATCH v9 3/5] dt-bindings: Document Loongson PCI Host Controller Jiaxun Yang
@ 2020-05-12  7:43   ` Jiaxun Yang
  2020-05-12  7:43   ` [PATCH v9 5/5] MIPS: Loongson64: Switch to generic PCI driver Jiaxun Yang
  3 siblings, 0 replies; 63+ messages in thread
From: Jiaxun Yang @ 2020-05-12  7:43 UTC (permalink / raw)
  To: linux-pci
  Cc: Jiaxun Yang, Bjorn Helgaas, Rob Herring, Thomas Bogendoerfer,
	Huacai Chen, Lorenzo Pieralisi, Paul Burton, devicetree,
	linux-kernel, linux-mips

Add PCI Host controller node for Loongson64 with RS780E PCH dts.
Note that PCI interrupts are probed via legacy way, as different
machine have different interrupt arrangement, we can't cover all
of them in dt.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 arch/mips/boot/dts/loongson/rs780e-pch.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/mips/boot/dts/loongson/rs780e-pch.dtsi b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
index 8687c4f7370a..d0d5d60a8697 100644
--- a/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
+++ b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
@@ -9,6 +9,18 @@ bus@10000000 {
 				0 0x40000000 0 0x40000000 0 0x40000000
 				0xfd 0xfe000000 0xfd 0xfe000000  0 0x2000000 /* PCI Config Space */>;
 
+		pci@1a000000 {
+			compatible = "loongson,rs780e-pci";
+			device_type = "pci";
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			reg = <0 0x1a000000 0 0x02000000>;
+
+			ranges = <0x01000000 0 0x00004000 0 0x18004000 0 0x00004000>,
+				 <0x02000000 0 0x40000000 0 0x40000000 0 0x40000000>;
+		};
+
 		isa {
 			compatible = "isa";
 			#address-cells = <2>;
-- 
2.26.2


^ permalink raw reply related	[flat|nested] 63+ messages in thread

* [PATCH v9 5/5] MIPS: Loongson64: Switch to generic PCI driver
  2020-05-12  7:43 ` [PATCH v9 1/5] PCI: Don't disable decoding when mmio_always_on is set Jiaxun Yang
                     ` (2 preceding siblings ...)
  2020-05-12  7:43   ` [PATCH v9 4/5] MIPS: DTS: Loongson64: Add PCI Controller Node Jiaxun Yang
@ 2020-05-12  7:43   ` Jiaxun Yang
  3 siblings, 0 replies; 63+ messages in thread
From: Jiaxun Yang @ 2020-05-12  7:43 UTC (permalink / raw)
  To: linux-pci
  Cc: Jiaxun Yang, Bjorn Helgaas, Rob Herring, Thomas Bogendoerfer,
	Huacai Chen, Lorenzo Pieralisi, Paul Burton, devicetree,
	linux-kernel, linux-mips

We can now enable generic PCI driver in Kconfig, and remove legacy
PCI driver code.

Radeon vbios quirk is moved to the platform folder to fit the
new structure.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
--
v9: Fix licenses tag
---
 arch/mips/Kconfig                  |   1 +
 arch/mips/loongson64/Makefile      |   2 +-
 arch/mips/loongson64/vbios_quirk.c |  29 ++++++++
 arch/mips/pci/Makefile             |   1 -
 arch/mips/pci/fixup-loongson3.c    |  71 ------------------
 arch/mips/pci/ops-loongson3.c      | 116 -----------------------------
 6 files changed, 31 insertions(+), 189 deletions(-)
 create mode 100644 arch/mips/loongson64/vbios_quirk.c
 delete mode 100644 arch/mips/pci/fixup-loongson3.c
 delete mode 100644 arch/mips/pci/ops-loongson3.c

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 0519ca9f00f9..7a4fcc4ade1f 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -480,6 +480,7 @@ config MACH_LOONGSON64
 	select IRQ_MIPS_CPU
 	select NR_CPUS_DEFAULT_64
 	select USE_GENERIC_EARLY_PRINTK_8250
+	select PCI_DRIVERS_GENERIC
 	select SYS_HAS_CPU_LOONGSON64
 	select SYS_HAS_EARLY_PRINTK
 	select SYS_SUPPORTS_SMP
diff --git a/arch/mips/loongson64/Makefile b/arch/mips/loongson64/Makefile
index 6f3c2b47f66f..6f81b822aeae 100644
--- a/arch/mips/loongson64/Makefile
+++ b/arch/mips/loongson64/Makefile
@@ -8,5 +8,5 @@ obj-$(CONFIG_MACH_LOONGSON64) += cop2-ex.o platform.o dma.o \
 obj-$(CONFIG_SMP)	+= smp.o
 obj-$(CONFIG_NUMA)	+= numa.o
 obj-$(CONFIG_RS780_HPET) += hpet.o
-obj-$(CONFIG_PCI) += pci.o
 obj-$(CONFIG_SUSPEND) += pm.o
+obj-$(CONFIG_PCI_QUIRKS) += vbios_quirk.o
diff --git a/arch/mips/loongson64/vbios_quirk.c b/arch/mips/loongson64/vbios_quirk.c
new file mode 100644
index 000000000000..9a29e94d3db1
--- /dev/null
+++ b/arch/mips/loongson64/vbios_quirk.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <linux/pci.h>
+#include <loongson.h>
+
+static void pci_fixup_radeon(struct pci_dev *pdev)
+{
+	struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
+
+	if (res->start)
+		return;
+
+	if (!loongson_sysconf.vgabios_addr)
+		return;
+
+	pci_disable_rom(pdev);
+	if (res->parent)
+		release_resource(res);
+
+	res->start = virt_to_phys((void *) loongson_sysconf.vgabios_addr);
+	res->end   = res->start + 256*1024 - 1;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ROM_SHADOW |
+		     IORESOURCE_PCI_FIXED;
+
+	dev_info(&pdev->dev, "BAR %d: assigned %pR for Radeon ROM\n",
+		 PCI_ROM_RESOURCE, res);
+}
+DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, 0x9615,
+				PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_radeon);
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 342ce10ef593..438f10955d89 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -35,7 +35,6 @@ obj-$(CONFIG_LASAT)		+= pci-lasat.o
 obj-$(CONFIG_MIPS_COBALT)	+= fixup-cobalt.o
 obj-$(CONFIG_LEMOTE_FULOONG2E)	+= fixup-fuloong2e.o ops-loongson2.o
 obj-$(CONFIG_LEMOTE_MACH2F)	+= fixup-lemote2f.o ops-loongson2.o
-obj-$(CONFIG_MACH_LOONGSON64)	+= fixup-loongson3.o ops-loongson3.o
 obj-$(CONFIG_MIPS_MALTA)	+= fixup-malta.o pci-malta.o
 obj-$(CONFIG_PMC_MSP7120_GW)	+= fixup-pmcmsp.o ops-pmcmsp.o
 obj-$(CONFIG_PMC_MSP7120_EVAL)	+= fixup-pmcmsp.o ops-pmcmsp.o
diff --git a/arch/mips/pci/fixup-loongson3.c b/arch/mips/pci/fixup-loongson3.c
deleted file mode 100644
index 8a741c2c6685..000000000000
--- a/arch/mips/pci/fixup-loongson3.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * fixup-loongson3.c
- *
- * Copyright (C) 2012 Lemote, Inc.
- * Author: Xiang Yu, xiangy@lemote.com
- *         Chen Huacai, chenhc@lemote.com
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- * THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- * WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- * NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- * USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-
-#include <linux/pci.h>
-#include <boot_param.h>
-
-static void print_fixup_info(const struct pci_dev *pdev)
-{
-	dev_info(&pdev->dev, "Device %x:%x, irq %d\n",
-			pdev->vendor, pdev->device, pdev->irq);
-}
-
-int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
-	print_fixup_info(dev);
-	return dev->irq;
-}
-
-static void pci_fixup_radeon(struct pci_dev *pdev)
-{
-	struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
-
-	if (res->start)
-		return;
-
-	if (!loongson_sysconf.vgabios_addr)
-		return;
-
-	pci_disable_rom(pdev);
-	if (res->parent)
-		release_resource(res);
-
-	res->start = virt_to_phys((void *) loongson_sysconf.vgabios_addr);
-	res->end   = res->start + 256*1024 - 1;
-	res->flags = IORESOURCE_MEM | IORESOURCE_ROM_SHADOW |
-		     IORESOURCE_PCI_FIXED;
-
-	dev_info(&pdev->dev, "BAR %d: assigned %pR for Radeon ROM\n",
-		 PCI_ROM_RESOURCE, res);
-}
-
-DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
-				PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_radeon);
-
-/* Do platform specific device initialization at pci_enable_device() time */
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
-	return 0;
-}
diff --git a/arch/mips/pci/ops-loongson3.c b/arch/mips/pci/ops-loongson3.c
deleted file mode 100644
index 2f6ad36bdea6..000000000000
--- a/arch/mips/pci/ops-loongson3.c
+++ /dev/null
@@ -1,116 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-
-#include <asm/mips-boards/bonito64.h>
-
-#include <loongson.h>
-
-#define PCI_ACCESS_READ  0
-#define PCI_ACCESS_WRITE 1
-
-#define HT1LO_PCICFG_BASE      0x1a000000
-#define HT1LO_PCICFG_BASE_TP1  0x1b000000
-
-static int loongson3_pci_config_access(unsigned char access_type,
-		struct pci_bus *bus, unsigned int devfn,
-		int where, u32 *data)
-{
-	unsigned char busnum = bus->number;
-	int function = PCI_FUNC(devfn);
-	int device = PCI_SLOT(devfn);
-	int reg = where & ~3;
-	void *addrp;
-	u64 addr;
-
-	if (where < PCI_CFG_SPACE_SIZE) { /* standard config */
-		addr = (busnum << 16) | (device << 11) | (function << 8) | reg;
-		if (busnum == 0) {
-			if (device > 31)
-				return PCIBIOS_DEVICE_NOT_FOUND;
-			addrp = (void *)TO_UNCAC(HT1LO_PCICFG_BASE | addr);
-		} else {
-			addrp = (void *)TO_UNCAC(HT1LO_PCICFG_BASE_TP1 | addr);
-		}
-	} else if (where < PCI_CFG_SPACE_EXP_SIZE) {  /* extended config */
-		struct pci_dev *rootdev;
-
-		rootdev = pci_get_domain_bus_and_slot(0, 0, 0);
-		if (!rootdev)
-			return PCIBIOS_DEVICE_NOT_FOUND;
-
-		addr = pci_resource_start(rootdev, 3);
-		if (!addr)
-			return PCIBIOS_DEVICE_NOT_FOUND;
-
-		addr |= busnum << 20 | device << 15 | function << 12 | reg;
-		addrp = (void *)TO_UNCAC(addr);
-	} else {
-		return PCIBIOS_DEVICE_NOT_FOUND;
-	}
-
-	if (access_type == PCI_ACCESS_WRITE)
-		writel(*data, addrp);
-	else {
-		*data = readl(addrp);
-		if (*data == 0xffffffff) {
-			*data = -1;
-			return PCIBIOS_DEVICE_NOT_FOUND;
-		}
-	}
-	return PCIBIOS_SUCCESSFUL;
-}
-
-static int loongson3_pci_pcibios_read(struct pci_bus *bus, unsigned int devfn,
-				 int where, int size, u32 *val)
-{
-	u32 data = 0;
-	int ret = loongson3_pci_config_access(PCI_ACCESS_READ,
-			bus, devfn, where, &data);
-
-	if (ret != PCIBIOS_SUCCESSFUL)
-		return ret;
-
-	if (size == 1)
-		*val = (data >> ((where & 3) << 3)) & 0xff;
-	else if (size == 2)
-		*val = (data >> ((where & 3) << 3)) & 0xffff;
-	else
-		*val = data;
-
-	return PCIBIOS_SUCCESSFUL;
-}
-
-static int loongson3_pci_pcibios_write(struct pci_bus *bus, unsigned int devfn,
-				  int where, int size, u32 val)
-{
-	u32 data = 0;
-	int ret;
-
-	if (size == 4)
-		data = val;
-	else {
-		ret = loongson3_pci_config_access(PCI_ACCESS_READ,
-				bus, devfn, where, &data);
-		if (ret != PCIBIOS_SUCCESSFUL)
-			return ret;
-
-		if (size == 1)
-			data = (data & ~(0xff << ((where & 3) << 3))) |
-			    (val << ((where & 3) << 3));
-		else if (size == 2)
-			data = (data & ~(0xffff << ((where & 3) << 3))) |
-			    (val << ((where & 3) << 3));
-	}
-
-	ret = loongson3_pci_config_access(PCI_ACCESS_WRITE,
-			bus, devfn, where, &data);
-
-	return ret;
-}
-
-struct pci_ops loongson_pci_ops = {
-	.read = loongson3_pci_pcibios_read,
-	.write = loongson3_pci_pcibios_write
-};
-- 
2.26.2


^ permalink raw reply related	[flat|nested] 63+ messages in thread

* Re: [PATCH v9 2/5] PCI: Add Loongson PCI Controller support
  2020-05-12  7:43   ` [PATCH v9 2/5] PCI: Add Loongson PCI Controller support Jiaxun Yang
@ 2020-05-12 18:06     ` Bjorn Helgaas
  2020-05-13  1:20       ` Jiaxun Yang
  0 siblings, 1 reply; 63+ messages in thread
From: Bjorn Helgaas @ 2020-05-12 18:06 UTC (permalink / raw)
  To: Jiaxun Yang
  Cc: linux-pci, Rob Herring, Bjorn Helgaas, Rob Herring,
	Thomas Bogendoerfer, Huacai Chen, Lorenzo Pieralisi, Paul Burton,
	devicetree, linux-kernel, linux-mips

On Tue, May 12, 2020 at 03:43:56PM +0800, Jiaxun Yang wrote:
> This controller can be found on Loongson-2K SoC, Loongson-3
> systems with RS780E/LS7A PCH.
> 
> The RS780E part of code was previously located at
> arch/mips/pci/ops-loongson3.c and now it can use generic PCI
> driver implementation.
> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Reviewed-by: Rob Herring <robh@kernel.org>

> +static void system_bus_quirk(struct pci_dev *pdev)
> +{
> +	u16 tmp;
> +
> +	/* 
> +	 * These devices are not sharing resouces with rest of devices
> +	 * on host bus and firmware will ensure their BARs are placed
> +	 * in safe ranges. Also there might be some config registers
> +	 * in their config space so kernel shouldn't ignore them.

"Firmware ensuring BARs are placed in 'safe' ranges" is not a
sufficient answer.  As I said before, Linux needs to know both the
ADDRESS and the SIZE of whatever non-standard BARs these are.
Otherwise, we're liable to assign that space to a different device.

If you have to hard-code the size, so be it.  That would mean the
hardware is completely broken, but at least we could make Linux deal
with it.  If the hardware consumes address space we don't know about,
we can't deal with that.

> +	 */
> +	pdev->mmio_always_on = 1;
> +	pdev->non_compliant_bars = 1;
> +}

> +void __iomem *pci_loongson_map_bus(struct pci_bus *bus, unsigned int devfn,
> +			       int where)
> +{
> +	unsigned char busnum = bus->number;
> +	struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
> +	struct loongson_pci *priv =  pci_host_bridge_priv(bridge);
> +
> +	/*
> +	 * Do not read more than one device on the bus other than
> +	 * the host bus 0.
> +	 */

If the hardware is restricted such that the root bus number must be
zero, pleae say that explicitly here.  Otherwise, it just looks like
a bug.

> +	if (priv->flags & FLAG_DEV_FIX && busnum != 0 &&
> +		PCI_SLOT(devfn) > 0)
> +		return NULL;
> +
> +	/* CFG0 can only access standard space */
> +	if (where < PCI_CFG_SPACE_SIZE && priv->cfg0_base)
> +		return cfg0_map(priv, busnum, devfn, where);
> +
> +	/* CFG1 can access extended space */
> +	if (where < PCI_CFG_SPACE_EXP_SIZE && priv->cfg1_base)
> +		return cfg1_map(priv, busnum, devfn, where);
> +
> +	return NULL;
> +}

^ permalink raw reply	[flat|nested] 63+ messages in thread

* Re: [PATCH v9 2/5] PCI: Add Loongson PCI Controller support
  2020-05-12 18:06     ` Bjorn Helgaas
@ 2020-05-13  1:20       ` Jiaxun Yang
  2020-05-13 15:05         ` Bjorn Helgaas
  0 siblings, 1 reply; 63+ messages in thread
From: Jiaxun Yang @ 2020-05-13  1:20 UTC (permalink / raw)
  To: Bjorn Helgaas
  Cc: linux-pci, Rob Herring, Bjorn Helgaas, Rob Herring,
	Thomas Bogendoerfer, Huacai Chen, Lorenzo Pieralisi, Paul Burton,
	devicetree, linux-kernel, linux-mips



于 2020年5月13日 GMT+08:00 上午2:06:02, Bjorn Helgaas <helgaas@kernel.org> 写到:
>On Tue, May 12, 2020 at 03:43:56PM +0800, Jiaxun Yang wrote:
>> This controller can be found on Loongson-2K SoC, Loongson-3
>> systems with RS780E/LS7A PCH.
>> 
>> The RS780E part of code was previously located at
>> arch/mips/pci/ops-loongson3.c and now it can use generic PCI
>> driver implementation.
>> 
>> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>> Reviewed-by: Rob Herring <robh@kernel.org>
>
>> +static void system_bus_quirk(struct pci_dev *pdev)
>> +{
>> +	u16 tmp;
>> +
>> +	/* 
>> +	 * These devices are not sharing resouces with rest of devices
>> +	 * on host bus and firmware will ensure their BARs are placed
>> +	 * in safe ranges. Also there might be some config registers
>> +	 * in their config space so kernel shouldn't ignore them.
>
>"Firmware ensuring BARs are placed in 'safe' ranges" is not a
>sufficient answer.  As I said before, Linux needs to know both the
>ADDRESS and the SIZE of whatever non-standard BARs these are.
>Otherwise, we're liable to assign that space to a different device.

The address assigned to these devices will never be a part of resources
belongs to the host bridge. That's enforced by hardware and firmware,
so address conflict would never happen.

I'm doing like this to ensure kernel will discover this device but do nothing
about assignment of resources to it.

>
>If you have to hard-code the size, so be it.  That would mean the
>hardware is completely broken, but at least we could make Linux deal
>with it.  If the hardware consumes address space we don't know about,
>we can't deal with that.
>
>> +	 */
>> +	pdev->mmio_always_on = 1;
>> +	pdev->non_compliant_bars = 1;
>> +}
>
>> +void __iomem *pci_loongson_map_bus(struct pci_bus *bus, unsigned int devfn,
>> +			       int where)
>> +{
>> +	unsigned char busnum = bus->number;
>> +	struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
>> +	struct loongson_pci *priv =  pci_host_bridge_priv(bridge);
>> +
>> +	/*
>> +	 * Do not read more than one device on the bus other than
>> +	 * the host bus 0.
>> +	 */
>
>If the hardware is restricted such that the root bus number must be
>zero, pleae say that explicitly here.  Otherwise, it just looks like
>a bug.
>
>> +	if (priv->flags & FLAG_DEV_FIX && busnum != 0 &&
>> +		PCI_SLOT(devfn) > 0)
>> +		return NULL;
>> +
>> +	/* CFG0 can only access standard space */
>> +	if (where < PCI_CFG_SPACE_SIZE && priv->cfg0_base)
>> +		return cfg0_map(priv, busnum, devfn, where);
>> +
>> +	/* CFG1 can access extended space */
>> +	if (where < PCI_CFG_SPACE_EXP_SIZE && priv->cfg1_base)
>> +		return cfg1_map(priv, busnum, devfn, where);
>> +
>> +	return NULL;
>> +}

-- 
Jiaxun Yang

^ permalink raw reply	[flat|nested] 63+ messages in thread

* Re: [PATCH v9 2/5] PCI: Add Loongson PCI Controller support
  2020-05-13  1:20       ` Jiaxun Yang
@ 2020-05-13 15:05         ` Bjorn Helgaas
  0 siblings, 0 replies; 63+ messages in thread
From: Bjorn Helgaas @ 2020-05-13 15:05 UTC (permalink / raw)
  To: Jiaxun Yang
  Cc: linux-pci, Rob Herring, Bjorn Helgaas, Rob Herring,
	Thomas Bogendoerfer, Huacai Chen, Lorenzo Pieralisi, Paul Burton,
	devicetree, linux-kernel, linux-mips

On Wed, May 13, 2020 at 09:20:08AM +0800, Jiaxun Yang wrote:
> 于 2020年5月13日 GMT+08:00 上午2:06:02, Bjorn Helgaas <helgaas@kernel.org> 写到:
> >On Tue, May 12, 2020 at 03:43:56PM +0800, Jiaxun Yang wrote:
> >> This controller can be found on Loongson-2K SoC, Loongson-3
> >> systems with RS780E/LS7A PCH.
> >> 
> >> The RS780E part of code was previously located at
> >> arch/mips/pci/ops-loongson3.c and now it can use generic PCI
> >> driver implementation.
> >> 
> >> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> >> Reviewed-by: Rob Herring <robh@kernel.org>
> >
> >> +static void system_bus_quirk(struct pci_dev *pdev)
> >> +{
> >> +	u16 tmp;
> >> +
> >> +	/* 
> >> +	 * These devices are not sharing resouces with rest of devices
> >> +	 * on host bus and firmware will ensure their BARs are placed
> >> +	 * in safe ranges. Also there might be some config registers
> >> +	 * in their config space so kernel shouldn't ignore them.
> >
> >"Firmware ensuring BARs are placed in 'safe' ranges" is not a
> >sufficient answer.  As I said before, Linux needs to know both the
> >ADDRESS and the SIZE of whatever non-standard BARs these are.
> >Otherwise, we're liable to assign that space to a different device.
> 
> The address assigned to these devices will never be a part of resources
> belongs to the host bridge. That's enforced by hardware and firmware,
> so address conflict would never happen.
> 
> I'm doing like this to ensure kernel will discover this device but do nothing
> about assignment of resources to it.

OK, that's really ugly, but I guess we can't do anything about it.  It
would be helpful to make the comment say something like:

  The address space consumed by these devices is outside the resources
  of the host bridge.

Side note: in ACPI systems, the ACPI namespace is supposed to describe
all resources consumed by all devices.  Does DT have a similar
expectation?  Is there something in DT that tells us about the address
space used by these devices?  Even if that space never overlaps with
the PCI host bridge apertures, it might be useful to show the space in
/proc/iomem and similar places.

Bjorn

^ permalink raw reply	[flat|nested] 63+ messages in thread

* [PATCH v10 1/5] PCI: Don't disable decoding when mmio_always_on is set
  2020-04-27  6:05 [PATCH v6 0/5] Loongson PCI Generic Driver Jiaxun Yang
                   ` (7 preceding siblings ...)
  2020-05-12  7:43 ` [PATCH v9 1/5] PCI: Don't disable decoding when mmio_always_on is set Jiaxun Yang
@ 2020-05-14 13:16 ` Jiaxun Yang
  2020-05-14 13:16   ` [PATCH v10 2/5] PCI: Add Loongson PCI Controller support Jiaxun Yang
                     ` (3 more replies)
  2020-05-26  9:21 ` [PATCH v11 0/5] Loongson Generic PCI v11 Jiaxun Yang
  9 siblings, 4 replies; 63+ messages in thread
From: Jiaxun Yang @ 2020-05-14 13:16 UTC (permalink / raw)
  To: linux-pci
  Cc: Jiaxun Yang, Bjorn Helgaas, Bjorn Helgaas, Rob Herring,
	Thomas Bogendoerfer, Huacai Chen, Lorenzo Pieralisi, Paul Burton,
	devicetree, linux-kernel, linux-mips

Don't disable MEM/IO decoding when a device have both non_compliant_bars
and mmio_always_on.

That would allow us quirk devices with junk in BARs but can't disable
their decoding.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Acked-by: Bjorn Helgaas <helgaas@kernel.org>
---
 drivers/pci/probe.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 77b8a145c39b..d9c2c3301a8a 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -1822,7 +1822,7 @@ int pci_setup_device(struct pci_dev *dev)
 	/* Device class may be changed after fixup */
 	class = dev->class >> 8;
 
-	if (dev->non_compliant_bars) {
+	if (dev->non_compliant_bars && !dev->mmio_always_on) {
 		pci_read_config_word(dev, PCI_COMMAND, &cmd);
 		if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
 			pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
-- 
2.26.2


^ permalink raw reply related	[flat|nested] 63+ messages in thread

* [PATCH v10 2/5] PCI: Add Loongson PCI Controller support
  2020-05-14 13:16 ` [PATCH v10 1/5] PCI: Don't disable decoding when mmio_always_on is set Jiaxun Yang
@ 2020-05-14 13:16   ` Jiaxun Yang
  2020-05-20 11:57     ` Jiaxun Yang
  2020-05-26  9:10     ` Lorenzo Pieralisi
  2020-05-14 13:16   ` [PATCH v10 3/5] dt-bindings: Document Loongson PCI Host Controller Jiaxun Yang
                     ` (2 subsequent siblings)
  3 siblings, 2 replies; 63+ messages in thread
From: Jiaxun Yang @ 2020-05-14 13:16 UTC (permalink / raw)
  To: linux-pci
  Cc: Jiaxun Yang, Rob Herring, Bjorn Helgaas, Rob Herring,
	Thomas Bogendoerfer, Huacai Chen, Lorenzo Pieralisi, Paul Burton,
	devicetree, linux-kernel, linux-mips

This controller can be found on Loongson-2K SoC, Loongson-3
systems with RS780E/LS7A PCH.

The RS780E part of code was previously located at
arch/mips/pci/ops-loongson3.c and now it can use generic PCI
driver implementation.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Rob Herring <robh@kernel.org>

--
v2:
	- Clean up according to rob's suggestions
	- Claim that it can't work as a module
v3:
	- Fix a typo
v4:
	- More clean-ups: Drop flag check, use devfn
v7:
	- Fix ordering according to huacai's suggestion
v8:
	- Style clean and bugfix according to Bjorn's review
v9:
	- Confirm with vendor about the details on system_bus BARs
	- Further cleanups
	- I think assume root_bus as 0 simplify our code a lot, as that's
		always valid to the hardware, as we're not ecam or dwc, we can't
		easily get host bus_nr via cfg, adding that will cause unnecessary
		overhead.

v10:
	- Enhance comments about system_bus quirk and host bus quirk.
---
 drivers/pci/controller/Kconfig        |  10 ++
 drivers/pci/controller/Makefile       |   1 +
 drivers/pci/controller/pci-loongson.c | 249 ++++++++++++++++++++++++++
 3 files changed, 260 insertions(+)
 create mode 100644 drivers/pci/controller/pci-loongson.c

diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 91bfdb784829..ae36edb1d7db 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -258,6 +258,16 @@ config PCI_HYPERV_INTERFACE
 	  The Hyper-V PCI Interface is a helper driver allows other drivers to
 	  have a common interface with the Hyper-V PCI frontend driver.
 
+config PCI_LOONGSON
+	bool "LOONGSON PCI Controller"
+	depends on MACH_LOONGSON64 || COMPILE_TEST
+	depends on OF
+	depends on PCI_QUIRKS
+	default MACH_LOONGSON64
+	help
+	  Say Y here if you want to enable PCI controller support on
+	  Loongson systems.
+
 source "drivers/pci/controller/dwc/Kconfig"
 source "drivers/pci/controller/mobiveil/Kconfig"
 source "drivers/pci/controller/cadence/Kconfig"
diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
index 158c59771824..fbac4b0190a0 100644
--- a/drivers/pci/controller/Makefile
+++ b/drivers/pci/controller/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
 obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
 obj-$(CONFIG_VMD) += vmd.o
 obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
+obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o
 # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
 obj-y				+= dwc/
 obj-y				+= mobiveil/
diff --git a/drivers/pci/controller/pci-loongson.c b/drivers/pci/controller/pci-loongson.c
new file mode 100644
index 000000000000..4879377b86f3
--- /dev/null
+++ b/drivers/pci/controller/pci-loongson.c
@@ -0,0 +1,249 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Loongson PCI Host Controller Driver
+ *
+ * Copyright (C) 2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
+ */
+
+#include <linux/of_device.h>
+#include <linux/of_pci.h>
+#include <linux/pci.h>
+#include <linux/pci_ids.h>
+
+#include "../pci.h"
+
+/* Device IDs */
+#define DEV_PCIE_PORT_0	0x7a09
+#define DEV_PCIE_PORT_1	0x7a19
+#define DEV_PCIE_PORT_2	0x7a29
+
+#define DEV_LS2K_APB	0x7a02
+#define DEV_LS7A_CONF	0x7a10
+#define DEV_LS7A_LPC	0x7a0c
+
+#define FLAG_CFG0	BIT(0)
+#define FLAG_CFG1	BIT(1)
+#define FLAG_DEV_FIX	BIT(2)
+
+struct loongson_pci {
+	void __iomem *cfg0_base;
+	void __iomem *cfg1_base;
+	struct platform_device *pdev;
+	u32 flags;
+};
+
+/* Fixup wrong class code in PCIe bridges */
+static void bridge_class_quirk(struct pci_dev *dev)
+{
+	dev->class = PCI_CLASS_BRIDGE_PCI << 8;
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON,
+			DEV_PCIE_PORT_0, bridge_class_quirk);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON,
+			DEV_PCIE_PORT_1, bridge_class_quirk);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON,
+			DEV_PCIE_PORT_2, bridge_class_quirk);
+
+static void system_bus_quirk(struct pci_dev *pdev)
+{
+	u16 tmp;
+
+	/* 
+	 * The address space consumed by these devices is outside the
+	 * resources of the host bridge.
+	 */
+	pdev->mmio_always_on = 1;
+	pdev->non_compliant_bars = 1;
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
+			DEV_LS2K_APB, system_bus_quirk);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
+			DEV_LS7A_CONF, system_bus_quirk);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
+			DEV_LS7A_LPC, system_bus_quirk);
+
+static void loongson_mrrs_quirk(struct pci_dev *dev)
+{
+	struct pci_bus *bus = dev->bus;
+	struct pci_dev *bridge;
+	static const struct pci_device_id bridge_devids[] = {
+		{ PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_0) },
+		{ PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_1) },
+		{ PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_2) },
+		{ 0, },
+	};
+
+	/* look for the matching bridge */
+	while (!pci_is_root_bus(bus)) {
+		bridge = bus->self;
+		bus = bus->parent;
+		/*
+		 * Some Loongson PCIe ports have a h/w limitation of
+		 * 256 bytes maximum read request size. They can't handle
+		 * anything larger than this. So force this limit on
+		 * any devices attached under these ports.
+		 */
+		if (pci_match_id(bridge_devids, bridge)) {
+			if (pcie_get_readrq(dev) > 256) {
+				pci_info(dev, "limiting MRRS to 256\n");
+				pcie_set_readrq(dev, 256);
+			}
+			break;
+		}
+	}
+}
+DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, loongson_mrrs_quirk);
+
+static void __iomem *cfg1_map(struct loongson_pci *priv, int bus,
+				unsigned int devfn, int where)
+{
+	unsigned long addroff = 0x0;
+
+	if (bus != 0)
+		addroff |= BIT(28); /* Type 1 Access */
+	addroff |= (where & 0xff) | ((where & 0xf00) << 16);
+	addroff |= (bus << 16) | (devfn << 8);
+	return priv->cfg1_base + addroff;
+}
+
+static void __iomem *cfg0_map(struct loongson_pci *priv, int bus,
+				unsigned int devfn, int where)
+{
+	unsigned long addroff = 0x0;
+
+	if (bus != 0)
+		addroff |= BIT(24); /* Type 1 Access */
+	addroff |= (bus << 16) | (devfn << 8) | where;
+	return priv->cfg0_base + addroff;
+}
+
+void __iomem *pci_loongson_map_bus(struct pci_bus *bus, unsigned int devfn,
+			       int where)
+{
+	unsigned char busnum = bus->number;
+	struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
+	struct loongson_pci *priv =  pci_host_bridge_priv(bridge);
+
+	/*
+	 * Do not read more than one device on the bus other than
+	 * the host bus. For our hardware the root bus is always bus 0.
+	 */
+	if (priv->flags & FLAG_DEV_FIX && busnum != 0 &&
+		PCI_SLOT(devfn) > 0)
+		return NULL;
+
+	/* CFG0 can only access standard space */
+	if (where < PCI_CFG_SPACE_SIZE && priv->cfg0_base)
+		return cfg0_map(priv, busnum, devfn, where);
+
+	/* CFG1 can access extended space */
+	if (where < PCI_CFG_SPACE_EXP_SIZE && priv->cfg1_base)
+		return cfg1_map(priv, busnum, devfn, where);
+
+	return NULL;
+}
+
+static int loongson_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+	int irq;
+	u8 val;
+
+	irq = of_irq_parse_and_map_pci(dev, slot, pin);
+	if (irq > 0)
+		return irq;
+
+	/* Care i8259 legacy systems */
+	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &val);
+	/* i8259 only have 15 IRQs */
+	if (val > 15)
+		return 0;
+
+	return val;
+}
+
+/* H/w only accept 32-bit PCI operations */
+static struct pci_ops loongson_pci_ops = {
+	.map_bus = pci_loongson_map_bus,
+	.read	= pci_generic_config_read32,
+	.write	= pci_generic_config_write32,
+};
+
+static const struct of_device_id loongson_pci_of_match[] = {
+	{ .compatible = "loongson,ls2k-pci",
+		.data = (void *)(FLAG_CFG0 | FLAG_CFG1 | FLAG_DEV_FIX), },
+	{ .compatible = "loongson,ls7a-pci",
+		.data = (void *)(FLAG_CFG0 | FLAG_CFG1 | FLAG_DEV_FIX), },
+	{ .compatible = "loongson,rs780e-pci",
+		.data = (void *)(FLAG_CFG0), },
+	{}
+};
+
+static int loongson_pci_probe(struct platform_device *pdev)
+{
+	struct loongson_pci *priv;
+	struct device *dev = &pdev->dev;
+	struct device_node *node = dev->of_node;
+	struct pci_host_bridge *bridge;
+	struct resource *regs;
+	int err;
+
+	if (!node)
+		return -ENODEV;
+
+	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*priv));
+	if (!bridge)
+		return -ENODEV;
+
+	priv = pci_host_bridge_priv(bridge);
+	priv->pdev = pdev;
+	priv->flags = (unsigned long)of_device_get_match_data(dev);
+
+	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!regs) {
+		dev_err(dev, "missing mem resources for cfg0\n");
+		return -EINVAL;
+	}
+
+	priv->cfg0_base = devm_pci_remap_cfg_resource(dev, regs);
+	if (IS_ERR(priv->cfg0_base))
+		return PTR_ERR(priv->cfg0_base);
+
+	/* CFG1 is optional */
+	if (priv->flags & FLAG_CFG1) {
+		regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+		if (!regs)
+			dev_info(dev, "missing mem resource for cfg1\n");
+		else {
+			priv->cfg1_base = devm_pci_remap_cfg_resource(dev, regs);
+			if (IS_ERR(priv->cfg1_base))
+				priv->cfg1_base = NULL;
+		}
+	}
+
+	err = pci_parse_request_of_pci_ranges(dev, &bridge->windows,
+						&bridge->dma_ranges, NULL);
+	if (err) {
+		dev_err(dev, "failed to get bridge resources\n");
+		return err;
+	}
+
+	bridge->dev.parent = dev;
+	bridge->sysdata = priv;
+	bridge->ops = &loongson_pci_ops;
+	bridge->map_irq = loongson_map_irq;
+
+	err = pci_host_probe(bridge);
+	if (err)
+		return err;
+
+	return 0;
+}
+
+static struct platform_driver loongson_pci_driver = {
+	.driver = {
+		.name = "loongson-pci",
+		.of_match_table = loongson_pci_of_match,
+	},
+	.probe = loongson_pci_probe,
+};
+builtin_platform_driver(loongson_pci_driver);
-- 
2.26.2


^ permalink raw reply related	[flat|nested] 63+ messages in thread

* [PATCH v10 3/5] dt-bindings: Document Loongson PCI Host Controller
  2020-05-14 13:16 ` [PATCH v10 1/5] PCI: Don't disable decoding when mmio_always_on is set Jiaxun Yang
  2020-05-14 13:16   ` [PATCH v10 2/5] PCI: Add Loongson PCI Controller support Jiaxun Yang
@ 2020-05-14 13:16   ` Jiaxun Yang
  2020-05-14 13:16   ` [PATCH v10 4/5] MIPS: DTS: Loongson64: Add PCI Controller Node Jiaxun Yang
  2020-05-14 13:16   ` [PATCH v10 5/5] MIPS: Loongson64: Switch to generic PCI driver Jiaxun Yang
  3 siblings, 0 replies; 63+ messages in thread
From: Jiaxun Yang @ 2020-05-14 13:16 UTC (permalink / raw)
  To: linux-pci
  Cc: Jiaxun Yang, Rob Herring, Bjorn Helgaas, Rob Herring,
	Thomas Bogendoerfer, Huacai Chen, Lorenzo Pieralisi, Paul Burton,
	devicetree, linux-kernel, linux-mips

PCI host controller found on Loongson PCHs and SoCs.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../devicetree/bindings/pci/loongson.yaml     | 62 +++++++++++++++++++
 1 file changed, 62 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/loongson.yaml

diff --git a/Documentation/devicetree/bindings/pci/loongson.yaml b/Documentation/devicetree/bindings/pci/loongson.yaml
new file mode 100644
index 000000000000..30e7cf1aeb87
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/loongson.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/loongson.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Loongson PCI Host Controller
+
+maintainers:
+  - Jiaxun Yang <jiaxun.yang@flygoat.com>
+
+description: |+
+  PCI host controller found on Loongson PCHs and SoCs.
+
+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+  compatible:
+    oneOf:
+      - const: loongson,ls2k-pci
+      - const: loongson,ls7a-pci
+      - const: loongson,rs780e-pci
+
+  reg:
+    minItems: 1
+    maxItems: 2
+    items:
+      - description: CFG0 standard config space register
+      - description: CFG1 extended config space register
+
+  ranges:
+    minItems: 1
+    maxItems: 3
+
+
+required:
+  - compatible
+  - reg
+  - ranges
+
+examples:
+  - |
+
+    bus {
+        #address-cells = <2>;
+        #size-cells = <2>;
+        pcie@1a000000 {
+            compatible = "loongson,rs780e-pci";
+            device_type = "pci";
+            #address-cells = <3>;
+            #size-cells = <2>;
+
+            // CPU_PHYSICAL(2)  SIZE(2)
+            reg = <0x0 0x1a000000  0x0 0x2000000>;
+
+            // BUS_ADDRESS(3)  CPU_PHYSICAL(2)  SIZE(2)
+            ranges = <0x01000000 0x0 0x00004000  0x0 0x00004000  0x0 0x00004000>,
+                     <0x02000000 0x0 0x40000000  0x0 0x40000000  0x0 0x40000000>;
+        };
+    };
+...
-- 
2.26.2


^ permalink raw reply related	[flat|nested] 63+ messages in thread

* [PATCH v10 4/5] MIPS: DTS: Loongson64: Add PCI Controller Node
  2020-05-14 13:16 ` [PATCH v10 1/5] PCI: Don't disable decoding when mmio_always_on is set Jiaxun Yang
  2020-05-14 13:16   ` [PATCH v10 2/5] PCI: Add Loongson PCI Controller support Jiaxun Yang
  2020-05-14 13:16   ` [PATCH v10 3/5] dt-bindings: Document Loongson PCI Host Controller Jiaxun Yang
@ 2020-05-14 13:16   ` Jiaxun Yang
  2020-05-22 14:25     ` Thomas Bogendoerfer
  2020-05-14 13:16   ` [PATCH v10 5/5] MIPS: Loongson64: Switch to generic PCI driver Jiaxun Yang
  3 siblings, 1 reply; 63+ messages in thread
From: Jiaxun Yang @ 2020-05-14 13:16 UTC (permalink / raw)
  To: linux-pci
  Cc: Jiaxun Yang, Bjorn Helgaas, Rob Herring, Thomas Bogendoerfer,
	Huacai Chen, Lorenzo Pieralisi, Paul Burton, devicetree,
	linux-kernel, linux-mips

Add PCI Host controller node for Loongson64 with RS780E PCH dts.
Note that PCI interrupts are probed via legacy way, as different
machine have different interrupt arrangement, we can't cover all
of them in dt.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 arch/mips/boot/dts/loongson/rs780e-pch.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/mips/boot/dts/loongson/rs780e-pch.dtsi b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
index 8687c4f7370a..d0d5d60a8697 100644
--- a/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
+++ b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
@@ -9,6 +9,18 @@ bus@10000000 {
 				0 0x40000000 0 0x40000000 0 0x40000000
 				0xfd 0xfe000000 0xfd 0xfe000000  0 0x2000000 /* PCI Config Space */>;
 
+		pci@1a000000 {
+			compatible = "loongson,rs780e-pci";
+			device_type = "pci";
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			reg = <0 0x1a000000 0 0x02000000>;
+
+			ranges = <0x01000000 0 0x00004000 0 0x18004000 0 0x00004000>,
+				 <0x02000000 0 0x40000000 0 0x40000000 0 0x40000000>;
+		};
+
 		isa {
 			compatible = "isa";
 			#address-cells = <2>;
-- 
2.26.2


^ permalink raw reply related	[flat|nested] 63+ messages in thread

* [PATCH v10 5/5] MIPS: Loongson64: Switch to generic PCI driver
  2020-05-14 13:16 ` [PATCH v10 1/5] PCI: Don't disable decoding when mmio_always_on is set Jiaxun Yang
                     ` (2 preceding siblings ...)
  2020-05-14 13:16   ` [PATCH v10 4/5] MIPS: DTS: Loongson64: Add PCI Controller Node Jiaxun Yang
@ 2020-05-14 13:16   ` Jiaxun Yang
  2020-05-22 14:25     ` Thomas Bogendoerfer
  3 siblings, 1 reply; 63+ messages in thread
From: Jiaxun Yang @ 2020-05-14 13:16 UTC (permalink / raw)
  To: linux-pci
  Cc: Jiaxun Yang, Bjorn Helgaas, Rob Herring, Thomas Bogendoerfer,
	Huacai Chen, Lorenzo Pieralisi, Paul Burton, devicetree,
	linux-kernel, linux-mips

We can now enable generic PCI driver in Kconfig, and remove legacy
PCI driver code.

Radeon vbios quirk is moved to the platform folder to fit the
new structure.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
--
v9: Fix licenses tag
---
 arch/mips/Kconfig                  |   1 +
 arch/mips/loongson64/Makefile      |   2 +-
 arch/mips/loongson64/vbios_quirk.c |  29 ++++++++
 arch/mips/pci/Makefile             |   1 -
 arch/mips/pci/fixup-loongson3.c    |  71 ------------------
 arch/mips/pci/ops-loongson3.c      | 116 -----------------------------
 6 files changed, 31 insertions(+), 189 deletions(-)
 create mode 100644 arch/mips/loongson64/vbios_quirk.c
 delete mode 100644 arch/mips/pci/fixup-loongson3.c
 delete mode 100644 arch/mips/pci/ops-loongson3.c

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 0519ca9f00f9..7a4fcc4ade1f 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -480,6 +480,7 @@ config MACH_LOONGSON64
 	select IRQ_MIPS_CPU
 	select NR_CPUS_DEFAULT_64
 	select USE_GENERIC_EARLY_PRINTK_8250
+	select PCI_DRIVERS_GENERIC
 	select SYS_HAS_CPU_LOONGSON64
 	select SYS_HAS_EARLY_PRINTK
 	select SYS_SUPPORTS_SMP
diff --git a/arch/mips/loongson64/Makefile b/arch/mips/loongson64/Makefile
index 6f3c2b47f66f..6f81b822aeae 100644
--- a/arch/mips/loongson64/Makefile
+++ b/arch/mips/loongson64/Makefile
@@ -8,5 +8,5 @@ obj-$(CONFIG_MACH_LOONGSON64) += cop2-ex.o platform.o dma.o \
 obj-$(CONFIG_SMP)	+= smp.o
 obj-$(CONFIG_NUMA)	+= numa.o
 obj-$(CONFIG_RS780_HPET) += hpet.o
-obj-$(CONFIG_PCI) += pci.o
 obj-$(CONFIG_SUSPEND) += pm.o
+obj-$(CONFIG_PCI_QUIRKS) += vbios_quirk.o
diff --git a/arch/mips/loongson64/vbios_quirk.c b/arch/mips/loongson64/vbios_quirk.c
new file mode 100644
index 000000000000..9a29e94d3db1
--- /dev/null
+++ b/arch/mips/loongson64/vbios_quirk.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <linux/pci.h>
+#include <loongson.h>
+
+static void pci_fixup_radeon(struct pci_dev *pdev)
+{
+	struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
+
+	if (res->start)
+		return;
+
+	if (!loongson_sysconf.vgabios_addr)
+		return;
+
+	pci_disable_rom(pdev);
+	if (res->parent)
+		release_resource(res);
+
+	res->start = virt_to_phys((void *) loongson_sysconf.vgabios_addr);
+	res->end   = res->start + 256*1024 - 1;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ROM_SHADOW |
+		     IORESOURCE_PCI_FIXED;
+
+	dev_info(&pdev->dev, "BAR %d: assigned %pR for Radeon ROM\n",
+		 PCI_ROM_RESOURCE, res);
+}
+DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, 0x9615,
+				PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_radeon);
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 342ce10ef593..438f10955d89 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -35,7 +35,6 @@ obj-$(CONFIG_LASAT)		+= pci-lasat.o
 obj-$(CONFIG_MIPS_COBALT)	+= fixup-cobalt.o
 obj-$(CONFIG_LEMOTE_FULOONG2E)	+= fixup-fuloong2e.o ops-loongson2.o
 obj-$(CONFIG_LEMOTE_MACH2F)	+= fixup-lemote2f.o ops-loongson2.o
-obj-$(CONFIG_MACH_LOONGSON64)	+= fixup-loongson3.o ops-loongson3.o
 obj-$(CONFIG_MIPS_MALTA)	+= fixup-malta.o pci-malta.o
 obj-$(CONFIG_PMC_MSP7120_GW)	+= fixup-pmcmsp.o ops-pmcmsp.o
 obj-$(CONFIG_PMC_MSP7120_EVAL)	+= fixup-pmcmsp.o ops-pmcmsp.o
diff --git a/arch/mips/pci/fixup-loongson3.c b/arch/mips/pci/fixup-loongson3.c
deleted file mode 100644
index 8a741c2c6685..000000000000
--- a/arch/mips/pci/fixup-loongson3.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * fixup-loongson3.c
- *
- * Copyright (C) 2012 Lemote, Inc.
- * Author: Xiang Yu, xiangy@lemote.com
- *         Chen Huacai, chenhc@lemote.com
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- * THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- * WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- * NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- * USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-
-#include <linux/pci.h>
-#include <boot_param.h>
-
-static void print_fixup_info(const struct pci_dev *pdev)
-{
-	dev_info(&pdev->dev, "Device %x:%x, irq %d\n",
-			pdev->vendor, pdev->device, pdev->irq);
-}
-
-int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
-	print_fixup_info(dev);
-	return dev->irq;
-}
-
-static void pci_fixup_radeon(struct pci_dev *pdev)
-{
-	struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
-
-	if (res->start)
-		return;
-
-	if (!loongson_sysconf.vgabios_addr)
-		return;
-
-	pci_disable_rom(pdev);
-	if (res->parent)
-		release_resource(res);
-
-	res->start = virt_to_phys((void *) loongson_sysconf.vgabios_addr);
-	res->end   = res->start + 256*1024 - 1;
-	res->flags = IORESOURCE_MEM | IORESOURCE_ROM_SHADOW |
-		     IORESOURCE_PCI_FIXED;
-
-	dev_info(&pdev->dev, "BAR %d: assigned %pR for Radeon ROM\n",
-		 PCI_ROM_RESOURCE, res);
-}
-
-DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
-				PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_radeon);
-
-/* Do platform specific device initialization at pci_enable_device() time */
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
-	return 0;
-}
diff --git a/arch/mips/pci/ops-loongson3.c b/arch/mips/pci/ops-loongson3.c
deleted file mode 100644
index 2f6ad36bdea6..000000000000
--- a/arch/mips/pci/ops-loongson3.c
+++ /dev/null
@@ -1,116 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-
-#include <asm/mips-boards/bonito64.h>
-
-#include <loongson.h>
-
-#define PCI_ACCESS_READ  0
-#define PCI_ACCESS_WRITE 1
-
-#define HT1LO_PCICFG_BASE      0x1a000000
-#define HT1LO_PCICFG_BASE_TP1  0x1b000000
-
-static int loongson3_pci_config_access(unsigned char access_type,
-		struct pci_bus *bus, unsigned int devfn,
-		int where, u32 *data)
-{
-	unsigned char busnum = bus->number;
-	int function = PCI_FUNC(devfn);
-	int device = PCI_SLOT(devfn);
-	int reg = where & ~3;
-	void *addrp;
-	u64 addr;
-
-	if (where < PCI_CFG_SPACE_SIZE) { /* standard config */
-		addr = (busnum << 16) | (device << 11) | (function << 8) | reg;
-		if (busnum == 0) {
-			if (device > 31)
-				return PCIBIOS_DEVICE_NOT_FOUND;
-			addrp = (void *)TO_UNCAC(HT1LO_PCICFG_BASE | addr);
-		} else {
-			addrp = (void *)TO_UNCAC(HT1LO_PCICFG_BASE_TP1 | addr);
-		}
-	} else if (where < PCI_CFG_SPACE_EXP_SIZE) {  /* extended config */
-		struct pci_dev *rootdev;
-
-		rootdev = pci_get_domain_bus_and_slot(0, 0, 0);
-		if (!rootdev)
-			return PCIBIOS_DEVICE_NOT_FOUND;
-
-		addr = pci_resource_start(rootdev, 3);
-		if (!addr)
-			return PCIBIOS_DEVICE_NOT_FOUND;
-
-		addr |= busnum << 20 | device << 15 | function << 12 | reg;
-		addrp = (void *)TO_UNCAC(addr);
-	} else {
-		return PCIBIOS_DEVICE_NOT_FOUND;
-	}
-
-	if (access_type == PCI_ACCESS_WRITE)
-		writel(*data, addrp);
-	else {
-		*data = readl(addrp);
-		if (*data == 0xffffffff) {
-			*data = -1;
-			return PCIBIOS_DEVICE_NOT_FOUND;
-		}
-	}
-	return PCIBIOS_SUCCESSFUL;
-}
-
-static int loongson3_pci_pcibios_read(struct pci_bus *bus, unsigned int devfn,
-				 int where, int size, u32 *val)
-{
-	u32 data = 0;
-	int ret = loongson3_pci_config_access(PCI_ACCESS_READ,
-			bus, devfn, where, &data);
-
-	if (ret != PCIBIOS_SUCCESSFUL)
-		return ret;
-
-	if (size == 1)
-		*val = (data >> ((where & 3) << 3)) & 0xff;
-	else if (size == 2)
-		*val = (data >> ((where & 3) << 3)) & 0xffff;
-	else
-		*val = data;
-
-	return PCIBIOS_SUCCESSFUL;
-}
-
-static int loongson3_pci_pcibios_write(struct pci_bus *bus, unsigned int devfn,
-				  int where, int size, u32 val)
-{
-	u32 data = 0;
-	int ret;
-
-	if (size == 4)
-		data = val;
-	else {
-		ret = loongson3_pci_config_access(PCI_ACCESS_READ,
-				bus, devfn, where, &data);
-		if (ret != PCIBIOS_SUCCESSFUL)
-			return ret;
-
-		if (size == 1)
-			data = (data & ~(0xff << ((where & 3) << 3))) |
-			    (val << ((where & 3) << 3));
-		else if (size == 2)
-			data = (data & ~(0xffff << ((where & 3) << 3))) |
-			    (val << ((where & 3) << 3));
-	}
-
-	ret = loongson3_pci_config_access(PCI_ACCESS_WRITE,
-			bus, devfn, where, &data);
-
-	return ret;
-}
-
-struct pci_ops loongson_pci_ops = {
-	.read = loongson3_pci_pcibios_read,
-	.write = loongson3_pci_pcibios_write
-};
-- 
2.26.2


^ permalink raw reply related	[flat|nested] 63+ messages in thread

* Re: [PATCH v10 2/5] PCI: Add Loongson PCI Controller support
  2020-05-14 13:16   ` [PATCH v10 2/5] PCI: Add Loongson PCI Controller support Jiaxun Yang
@ 2020-05-20 11:57     ` Jiaxun Yang
  2020-05-22 13:10       ` Lorenzo Pieralisi
  2020-05-26  9:10     ` Lorenzo Pieralisi
  1 sibling, 1 reply; 63+ messages in thread
From: Jiaxun Yang @ 2020-05-20 11:57 UTC (permalink / raw)
  To: linux-pci
  Cc: Rob Herring, Bjorn Helgaas, Rob Herring, Thomas Bogendoerfer,
	Huacai Chen, Lorenzo Pieralisi, Paul Burton, devicetree,
	linux-kernel, linux-mips



于 2020年5月14日 GMT+08:00 下午9:16:38, Jiaxun Yang <jiaxun.yang@flygoat.com> 写到:
>This controller can be found on Loongson-2K SoC, Loongson-3
>systems with RS780E/LS7A PCH.
>
>The RS780E part of code was previously located at
>arch/mips/pci/ops-loongson3.c and now it can use generic PCI
>driver implementation.
>
>Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>Reviewed-by: Rob Herring <robh@kernel.org>
>

Hi there,

Is it possible to let this series go into next tree soon?

As LS7A dts patch would depend on this series, and I want to
make the whole LS7A basic support as a part of 5.8 release.

Thanks!

-- 
Jiaxun Yang

^ permalink raw reply	[flat|nested] 63+ messages in thread

* Re: [PATCH v7 1/5] PCI: Don't disable decoding when mmio_always_on is set
  2020-04-28  1:14   ` [PATCH v7 1/5] PCI: Don't disable decoding when mmio_always_on is set Jiaxun Yang
  2020-05-08 18:51     ` Bjorn Helgaas
@ 2020-05-20 20:55     ` Rob Herring
  1 sibling, 0 replies; 63+ messages in thread
From: Rob Herring @ 2020-05-20 20:55 UTC (permalink / raw)
  To: Jiaxun Yang
  Cc: Huacai Chen, linux-mips, linux-kernel, devicetree,
	Thomas Bogendoerfer, Lorenzo Pieralisi, linux-pci, Rob Herring,
	Paul Burton, Bjorn Helgaas

On Tue, 28 Apr 2020 09:14:16 +0800, Jiaxun Yang wrote:
> Don't disable MEM/IO decoding when a device have both non_compliant_bars
> and mmio_always_on.
> 
> That would allow us quirk devices with junk in BARs but can't disable
> their decoding.
> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
>  drivers/pci/probe.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Acked-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 63+ messages in thread

* Re: [PATCH v10 2/5] PCI: Add Loongson PCI Controller support
  2020-05-20 11:57     ` Jiaxun Yang
@ 2020-05-22 13:10       ` Lorenzo Pieralisi
  2020-05-22 13:32         ` Jiaxun Yang
  0 siblings, 1 reply; 63+ messages in thread
From: Lorenzo Pieralisi @ 2020-05-22 13:10 UTC (permalink / raw)
  To: Jiaxun Yang
  Cc: linux-pci, Rob Herring, Bjorn Helgaas, Rob Herring,
	Thomas Bogendoerfer, Huacai Chen, Paul Burton, devicetree,
	linux-kernel, linux-mips

On Wed, May 20, 2020 at 07:57:29PM +0800, Jiaxun Yang wrote:
> 
> 
> 于 2020年5月14日 GMT+08:00 下午9:16:38, Jiaxun Yang <jiaxun.yang@flygoat.com> 写到:
> >This controller can be found on Loongson-2K SoC, Loongson-3
> >systems with RS780E/LS7A PCH.
> >
> >The RS780E part of code was previously located at
> >arch/mips/pci/ops-loongson3.c and now it can use generic PCI
> >driver implementation.
> >
> >Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> >Reviewed-by: Rob Herring <robh@kernel.org>
> >
> 
> Hi there,
> 
> Is it possible to let this series go into next tree soon?
> 
> As LS7A dts patch would depend on this series, and I want to
> make the whole LS7A basic support as a part of 5.8 release.

I think you have all necessary tags to take this in the MIPS
tree, please let me know if that's the way we want this to go
upstream - I would not pull MIPS/dts changes into the PCI tree
and I don't think it is needed for this series.

Thanks,
Lorenzo

^ permalink raw reply	[flat|nested] 63+ messages in thread

* Re: [PATCH v10 2/5] PCI: Add Loongson PCI Controller support
  2020-05-22 13:10       ` Lorenzo Pieralisi
@ 2020-05-22 13:32         ` Jiaxun Yang
  2020-05-22 13:40           ` Lorenzo Pieralisi
  2020-05-22 14:27           ` Thomas Bogendoerfer
  0 siblings, 2 replies; 63+ messages in thread
From: Jiaxun Yang @ 2020-05-22 13:32 UTC (permalink / raw)
  To: Lorenzo Pieralisi
  Cc: linux-pci, Rob Herring, Bjorn Helgaas, Rob Herring,
	Thomas Bogendoerfer, Huacai Chen, Paul Burton, devicetree,
	linux-kernel, linux-mips



于 2020年5月22日 GMT+08:00 下午9:10:18, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> 写到:
>On Wed, May 20, 2020 at 07:57:29PM +0800, Jiaxun Yang wrote:
>> 
>> 
>> 于 2020年5月14日 GMT+08:00 下午9:16:38, Jiaxun Yang <jiaxun.yang@flygoat.com> 写到:
>> >This controller can be found on Loongson-2K SoC, Loongson-3
>> >systems with RS780E/LS7A PCH.
>> >
>> >The RS780E part of code was previously located at
>> >arch/mips/pci/ops-loongson3.c and now it can use generic PCI
>> >driver implementation.
>> >
>> >Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>> >Reviewed-by: Rob Herring <robh@kernel.org>
>> >
>> 
>> Hi there,
>> 
>> Is it possible to let this series go into next tree soon?
>> 
>> As LS7A dts patch would depend on this series, and I want to
>> make the whole LS7A basic support as a part of 5.8 release.
>
>I think you have all necessary tags to take this in the MIPS
>tree, please let me know if that's the way we want this to go
>upstream - I would not pull MIPS/dts changes into the PCI tree
>and I don't think it is needed for this series.

Please pull all PCI changes [1~3] into PCI tree.

And Thomas,
Could you please apply rest changes into MIPS Tree?

Thanks a lot!

>
>Thanks,
>Lorenzo

-- 
Jiaxun Yang

^ permalink raw reply	[flat|nested] 63+ messages in thread

* Re: [PATCH v10 2/5] PCI: Add Loongson PCI Controller support
  2020-05-22 13:32         ` Jiaxun Yang
@ 2020-05-22 13:40           ` Lorenzo Pieralisi
  2020-05-22 14:27             ` Thomas Bogendoerfer
  2020-05-22 14:27           ` Thomas Bogendoerfer
  1 sibling, 1 reply; 63+ messages in thread
From: Lorenzo Pieralisi @ 2020-05-22 13:40 UTC (permalink / raw)
  To: Jiaxun Yang
  Cc: linux-pci, Rob Herring, Bjorn Helgaas, Rob Herring,
	Thomas Bogendoerfer, Huacai Chen, Paul Burton, devicetree,
	linux-kernel, linux-mips

On Fri, May 22, 2020 at 09:32:10PM +0800, Jiaxun Yang wrote:

[...]

> >> Is it possible to let this series go into next tree soon?
> >> 
> >> As LS7A dts patch would depend on this series, and I want to
> >> make the whole LS7A basic support as a part of 5.8 release.
> >
> >I think you have all necessary tags to take this in the MIPS
> >tree, please let me know if that's the way we want this to go
> >upstream - I would not pull MIPS/dts changes into the PCI tree
> >and I don't think it is needed for this series.
> 
> Please pull all PCI changes [1~3] into PCI tree.

Pulled [1,2,3] into pci/mips, thanks !

Lorenzo

^ permalink raw reply	[flat|nested] 63+ messages in thread

* Re: [PATCH v10 4/5] MIPS: DTS: Loongson64: Add PCI Controller Node
  2020-05-14 13:16   ` [PATCH v10 4/5] MIPS: DTS: Loongson64: Add PCI Controller Node Jiaxun Yang
@ 2020-05-22 14:25     ` Thomas Bogendoerfer
  0 siblings, 0 replies; 63+ messages in thread
From: Thomas Bogendoerfer @ 2020-05-22 14:25 UTC (permalink / raw)
  To: Jiaxun Yang
  Cc: linux-pci, Bjorn Helgaas, Rob Herring, Huacai Chen,
	Lorenzo Pieralisi, Paul Burton, devicetree, linux-kernel,
	linux-mips

On Thu, May 14, 2020 at 09:16:40PM +0800, Jiaxun Yang wrote:
> Add PCI Host controller node for Loongson64 with RS780E PCH dts.
> Note that PCI interrupts are probed via legacy way, as different
> machine have different interrupt arrangement, we can't cover all
> of them in dt.
> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
>  arch/mips/boot/dts/loongson/rs780e-pch.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)

Acked-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

^ permalink raw reply	[flat|nested] 63+ messages in thread

* Re: [PATCH v10 5/5] MIPS: Loongson64: Switch to generic PCI driver
  2020-05-14 13:16   ` [PATCH v10 5/5] MIPS: Loongson64: Switch to generic PCI driver Jiaxun Yang
@ 2020-05-22 14:25     ` Thomas Bogendoerfer
  2020-05-22 15:22       ` Lorenzo Pieralisi
  0 siblings, 1 reply; 63+ messages in thread
From: Thomas Bogendoerfer @ 2020-05-22 14:25 UTC (permalink / raw)
  To: Jiaxun Yang
  Cc: linux-pci, Bjorn Helgaas, Rob Herring, Huacai Chen,
	Lorenzo Pieralisi, Paul Burton, devicetree, linux-kernel,
	linux-mips

On Thu, May 14, 2020 at 09:16:41PM +0800, Jiaxun Yang wrote:
> We can now enable generic PCI driver in Kconfig, and remove legacy
> PCI driver code.
> 
> Radeon vbios quirk is moved to the platform folder to fit the
> new structure.
> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> --
> v9: Fix licenses tag
> ---
>  arch/mips/Kconfig                  |   1 +
>  arch/mips/loongson64/Makefile      |   2 +-
>  arch/mips/loongson64/vbios_quirk.c |  29 ++++++++
>  arch/mips/pci/Makefile             |   1 -
>  arch/mips/pci/fixup-loongson3.c    |  71 ------------------
>  arch/mips/pci/ops-loongson3.c      | 116 -----------------------------
>  6 files changed, 31 insertions(+), 189 deletions(-)
>  create mode 100644 arch/mips/loongson64/vbios_quirk.c
>  delete mode 100644 arch/mips/pci/fixup-loongson3.c
>  delete mode 100644 arch/mips/pci/ops-loongson3.c

Acked-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

^ permalink raw reply	[flat|nested] 63+ messages in thread

* Re: [PATCH v10 2/5] PCI: Add Loongson PCI Controller support
  2020-05-22 13:32         ` Jiaxun Yang
  2020-05-22 13:40           ` Lorenzo Pieralisi
@ 2020-05-22 14:27           ` Thomas Bogendoerfer
  1 sibling, 0 replies; 63+ messages in thread
From: Thomas Bogendoerfer @ 2020-05-22 14:27 UTC (permalink / raw)
  To: Jiaxun Yang
  Cc: Lorenzo Pieralisi, linux-pci, Rob Herring, Bjorn Helgaas,
	Rob Herring, Huacai Chen, Paul Burton, devicetree, linux-kernel,
	linux-mips

On Fri, May 22, 2020 at 09:32:10PM +0800, Jiaxun Yang wrote:
> 
> 
> 于 2020年5月22日 GMT+08:00 下午9:10:18, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> 写到:
> >On Wed, May 20, 2020 at 07:57:29PM +0800, Jiaxun Yang wrote:
> >> 
> >> 
> >> 于 2020年5月14日 GMT+08:00 下午9:16:38, Jiaxun Yang <jiaxun.yang@flygoat.com> 写到:
> >> >This controller can be found on Loongson-2K SoC, Loongson-3
> >> >systems with RS780E/LS7A PCH.
> >> >
> >> >The RS780E part of code was previously located at
> >> >arch/mips/pci/ops-loongson3.c and now it can use generic PCI
> >> >driver implementation.
> >> >
> >> >Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> >> >Reviewed-by: Rob Herring <robh@kernel.org>
> >> >
> >> 
> >> Hi there,
> >> 
> >> Is it possible to let this series go into next tree soon?
> >> 
> >> As LS7A dts patch would depend on this series, and I want to
> >> make the whole LS7A basic support as a part of 5.8 release.
> >
> >I think you have all necessary tags to take this in the MIPS
> >tree, please let me know if that's the way we want this to go
> >upstream - I would not pull MIPS/dts changes into the PCI tree
> >and I don't think it is needed for this series.
> 
> Please pull all PCI changes [1~3] into PCI tree.
> 
> And Thomas,
> Could you please apply rest changes into MIPS Tree?

this will cause loss of PCI support for loongson in mips-next until
everything is pulled together during merge window. As this isn't too
nice I've acked the remaining patches to get them into the pci/mips
tree, too.

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

^ permalink raw reply	[flat|nested] 63+ messages in thread

* Re: [PATCH v10 2/5] PCI: Add Loongson PCI Controller support
  2020-05-22 13:40           ` Lorenzo Pieralisi
@ 2020-05-22 14:27             ` Thomas Bogendoerfer
  0 siblings, 0 replies; 63+ messages in thread
From: Thomas Bogendoerfer @ 2020-05-22 14:27 UTC (permalink / raw)
  To: Lorenzo Pieralisi
  Cc: Jiaxun Yang, linux-pci, Rob Herring, Bjorn Helgaas, Rob Herring,
	Huacai Chen, Paul Burton, devicetree, linux-kernel, linux-mips

On Fri, May 22, 2020 at 02:40:48PM +0100, Lorenzo Pieralisi wrote:
> On Fri, May 22, 2020 at 09:32:10PM +0800, Jiaxun Yang wrote:
> 
> [...]
> 
> > >> Is it possible to let this series go into next tree soon?
> > >> 
> > >> As LS7A dts patch would depend on this series, and I want to
> > >> make the whole LS7A basic support as a part of 5.8 release.
> > >
> > >I think you have all necessary tags to take this in the MIPS
> > >tree, please let me know if that's the way we want this to go
> > >upstream - I would not pull MIPS/dts changes into the PCI tree
> > >and I don't think it is needed for this series.
> > 
> > Please pull all PCI changes [1~3] into PCI tree.
> 
> Pulled [1,2,3] into pci/mips, thanks !

could please take the other patches, too ?

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

^ permalink raw reply	[flat|nested] 63+ messages in thread

* Re: [PATCH v10 5/5] MIPS: Loongson64: Switch to generic PCI driver
  2020-05-22 14:25     ` Thomas Bogendoerfer
@ 2020-05-22 15:22       ` Lorenzo Pieralisi
  2020-05-22 22:36         ` Thomas Bogendoerfer
  0 siblings, 1 reply; 63+ messages in thread
From: Lorenzo Pieralisi @ 2020-05-22 15:22 UTC (permalink / raw)
  To: Thomas Bogendoerfer
  Cc: Jiaxun Yang, linux-pci, Bjorn Helgaas, Rob Herring, Huacai Chen,
	Paul Burton, devicetree, linux-kernel, linux-mips

On Fri, May 22, 2020 at 04:25:50PM +0200, Thomas Bogendoerfer wrote:
> On Thu, May 14, 2020 at 09:16:41PM +0800, Jiaxun Yang wrote:
> > We can now enable generic PCI driver in Kconfig, and remove legacy
> > PCI driver code.
> > 
> > Radeon vbios quirk is moved to the platform folder to fit the
> > new structure.
> > 
> > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> > --
> > v9: Fix licenses tag
> > ---
> >  arch/mips/Kconfig                  |   1 +
> >  arch/mips/loongson64/Makefile      |   2 +-
> >  arch/mips/loongson64/vbios_quirk.c |  29 ++++++++
> >  arch/mips/pci/Makefile             |   1 -
> >  arch/mips/pci/fixup-loongson3.c    |  71 ------------------
> >  arch/mips/pci/ops-loongson3.c      | 116 -----------------------------
> >  6 files changed, 31 insertions(+), 189 deletions(-)
> >  create mode 100644 arch/mips/loongson64/vbios_quirk.c
> >  delete mode 100644 arch/mips/pci/fixup-loongson3.c
> >  delete mode 100644 arch/mips/pci/ops-loongson3.c
> 
> Acked-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

This patch (so the series) does not apply to v5.7-rc1 which is our
baseline. I reiterate the point, isn't it better to take the whole
series through the MIPS tree ? Failing that, the series has to
be rebased (or split differently so that it can be taken through
different trees), just let me know.

Thanks,
Lorenzo

^ permalink raw reply	[flat|nested] 63+ messages in thread

* Re: [PATCH v10 5/5] MIPS: Loongson64: Switch to generic PCI driver
  2020-05-22 15:22       ` Lorenzo Pieralisi
@ 2020-05-22 22:36         ` Thomas Bogendoerfer
  2020-05-26  9:12           ` Lorenzo Pieralisi
  0 siblings, 1 reply; 63+ messages in thread
From: Thomas Bogendoerfer @ 2020-05-22 22:36 UTC (permalink / raw)
  To: Lorenzo Pieralisi
  Cc: Jiaxun Yang, linux-pci, Bjorn Helgaas, Rob Herring, Huacai Chen,
	Paul Burton, devicetree, linux-kernel, linux-mips

On Fri, May 22, 2020 at 04:22:11PM +0100, Lorenzo Pieralisi wrote:
> On Fri, May 22, 2020 at 04:25:50PM +0200, Thomas Bogendoerfer wrote:
> > On Thu, May 14, 2020 at 09:16:41PM +0800, Jiaxun Yang wrote:
> > > We can now enable generic PCI driver in Kconfig, and remove legacy
> > > PCI driver code.
> > > 
> > > Radeon vbios quirk is moved to the platform folder to fit the
> > > new structure.
> > > 
> > > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> > > --
> > > v9: Fix licenses tag
> > > ---
> > >  arch/mips/Kconfig                  |   1 +
> > >  arch/mips/loongson64/Makefile      |   2 +-
> > >  arch/mips/loongson64/vbios_quirk.c |  29 ++++++++
> > >  arch/mips/pci/Makefile             |   1 -
> > >  arch/mips/pci/fixup-loongson3.c    |  71 ------------------
> > >  arch/mips/pci/ops-loongson3.c      | 116 -----------------------------
> > >  6 files changed, 31 insertions(+), 189 deletions(-)
> > >  create mode 100644 arch/mips/loongson64/vbios_quirk.c
> > >  delete mode 100644 arch/mips/pci/fixup-loongson3.c
> > >  delete mode 100644 arch/mips/pci/ops-loongson3.c
> > 
> > Acked-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> 
> This patch (so the series) does not apply to v5.7-rc1 which is our
> baseline. I reiterate the point, isn't it better to take the whole
> series through the MIPS tree ?

sounds better then

> Failing that, the series has to
> be rebased (or split differently so that it can be taken through
> different trees), just let me know.

so let's take via mips-next. So can I add your Acked-by to the
first three patches ?

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

^ permalink raw reply	[flat|nested] 63+ messages in thread

* Re: [PATCH v10 2/5] PCI: Add Loongson PCI Controller support
  2020-05-14 13:16   ` [PATCH v10 2/5] PCI: Add Loongson PCI Controller support Jiaxun Yang
  2020-05-20 11:57     ` Jiaxun Yang
@ 2020-05-26  9:10     ` Lorenzo Pieralisi
  1 sibling, 0 replies; 63+ messages in thread
From: Lorenzo Pieralisi @ 2020-05-26  9:10 UTC (permalink / raw)
  To: Jiaxun Yang
  Cc: linux-pci, Rob Herring, Bjorn Helgaas, Rob Herring,
	Thomas Bogendoerfer, Huacai Chen, Paul Burton, devicetree,
	linux-kernel, linux-mips

On Thu, May 14, 2020 at 09:16:38PM +0800, Jiaxun Yang wrote:
> This controller can be found on Loongson-2K SoC, Loongson-3
> systems with RS780E/LS7A PCH.
> 
> The RS780E part of code was previously located at
> arch/mips/pci/ops-loongson3.c and now it can use generic PCI
> driver implementation.
> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> 
> --
> v2:
> 	- Clean up according to rob's suggestions
> 	- Claim that it can't work as a module
> v3:
> 	- Fix a typo
> v4:
> 	- More clean-ups: Drop flag check, use devfn
> v7:
> 	- Fix ordering according to huacai's suggestion
> v8:
> 	- Style clean and bugfix according to Bjorn's review
> v9:
> 	- Confirm with vendor about the details on system_bus BARs
> 	- Further cleanups
> 	- I think assume root_bus as 0 simplify our code a lot, as that's
> 		always valid to the hardware, as we're not ecam or dwc, we can't
> 		easily get host bus_nr via cfg, adding that will cause unnecessary
> 		overhead.
> 
> v10:
> 	- Enhance comments about system_bus quirk and host bus quirk.
> ---
>  drivers/pci/controller/Kconfig        |  10 ++
>  drivers/pci/controller/Makefile       |   1 +
>  drivers/pci/controller/pci-loongson.c | 249 ++++++++++++++++++++++++++
>  3 files changed, 260 insertions(+)
>  create mode 100644 drivers/pci/controller/pci-loongson.c

Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

> diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> index 91bfdb784829..ae36edb1d7db 100644
> --- a/drivers/pci/controller/Kconfig
> +++ b/drivers/pci/controller/Kconfig
> @@ -258,6 +258,16 @@ config PCI_HYPERV_INTERFACE
>  	  The Hyper-V PCI Interface is a helper driver allows other drivers to
>  	  have a common interface with the Hyper-V PCI frontend driver.
>  
> +config PCI_LOONGSON
> +	bool "LOONGSON PCI Controller"
> +	depends on MACH_LOONGSON64 || COMPILE_TEST
> +	depends on OF
> +	depends on PCI_QUIRKS
> +	default MACH_LOONGSON64
> +	help
> +	  Say Y here if you want to enable PCI controller support on
> +	  Loongson systems.
> +
>  source "drivers/pci/controller/dwc/Kconfig"
>  source "drivers/pci/controller/mobiveil/Kconfig"
>  source "drivers/pci/controller/cadence/Kconfig"
> diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
> index 158c59771824..fbac4b0190a0 100644
> --- a/drivers/pci/controller/Makefile
> +++ b/drivers/pci/controller/Makefile
> @@ -28,6 +28,7 @@ obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
>  obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
>  obj-$(CONFIG_VMD) += vmd.o
>  obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
> +obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o
>  # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
>  obj-y				+= dwc/
>  obj-y				+= mobiveil/
> diff --git a/drivers/pci/controller/pci-loongson.c b/drivers/pci/controller/pci-loongson.c
> new file mode 100644
> index 000000000000..4879377b86f3
> --- /dev/null
> +++ b/drivers/pci/controller/pci-loongson.c
> @@ -0,0 +1,249 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Loongson PCI Host Controller Driver
> + *
> + * Copyright (C) 2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
> + */
> +
> +#include <linux/of_device.h>
> +#include <linux/of_pci.h>
> +#include <linux/pci.h>
> +#include <linux/pci_ids.h>
> +
> +#include "../pci.h"
> +
> +/* Device IDs */
> +#define DEV_PCIE_PORT_0	0x7a09
> +#define DEV_PCIE_PORT_1	0x7a19
> +#define DEV_PCIE_PORT_2	0x7a29
> +
> +#define DEV_LS2K_APB	0x7a02
> +#define DEV_LS7A_CONF	0x7a10
> +#define DEV_LS7A_LPC	0x7a0c
> +
> +#define FLAG_CFG0	BIT(0)
> +#define FLAG_CFG1	BIT(1)
> +#define FLAG_DEV_FIX	BIT(2)
> +
> +struct loongson_pci {
> +	void __iomem *cfg0_base;
> +	void __iomem *cfg1_base;
> +	struct platform_device *pdev;
> +	u32 flags;
> +};
> +
> +/* Fixup wrong class code in PCIe bridges */
> +static void bridge_class_quirk(struct pci_dev *dev)
> +{
> +	dev->class = PCI_CLASS_BRIDGE_PCI << 8;
> +}
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON,
> +			DEV_PCIE_PORT_0, bridge_class_quirk);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON,
> +			DEV_PCIE_PORT_1, bridge_class_quirk);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON,
> +			DEV_PCIE_PORT_2, bridge_class_quirk);
> +
> +static void system_bus_quirk(struct pci_dev *pdev)
> +{
> +	u16 tmp;
> +
> +	/* 
> +	 * The address space consumed by these devices is outside the
> +	 * resources of the host bridge.
> +	 */
> +	pdev->mmio_always_on = 1;
> +	pdev->non_compliant_bars = 1;
> +}
> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
> +			DEV_LS2K_APB, system_bus_quirk);
> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
> +			DEV_LS7A_CONF, system_bus_quirk);
> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
> +			DEV_LS7A_LPC, system_bus_quirk);
> +
> +static void loongson_mrrs_quirk(struct pci_dev *dev)
> +{
> +	struct pci_bus *bus = dev->bus;
> +	struct pci_dev *bridge;
> +	static const struct pci_device_id bridge_devids[] = {
> +		{ PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_0) },
> +		{ PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_1) },
> +		{ PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_2) },
> +		{ 0, },
> +	};
> +
> +	/* look for the matching bridge */
> +	while (!pci_is_root_bus(bus)) {
> +		bridge = bus->self;
> +		bus = bus->parent;
> +		/*
> +		 * Some Loongson PCIe ports have a h/w limitation of
> +		 * 256 bytes maximum read request size. They can't handle
> +		 * anything larger than this. So force this limit on
> +		 * any devices attached under these ports.
> +		 */
> +		if (pci_match_id(bridge_devids, bridge)) {
> +			if (pcie_get_readrq(dev) > 256) {
> +				pci_info(dev, "limiting MRRS to 256\n");
> +				pcie_set_readrq(dev, 256);
> +			}
> +			break;
> +		}
> +	}
> +}
> +DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, loongson_mrrs_quirk);
> +
> +static void __iomem *cfg1_map(struct loongson_pci *priv, int bus,
> +				unsigned int devfn, int where)
> +{
> +	unsigned long addroff = 0x0;
> +
> +	if (bus != 0)
> +		addroff |= BIT(28); /* Type 1 Access */
> +	addroff |= (where & 0xff) | ((where & 0xf00) << 16);
> +	addroff |= (bus << 16) | (devfn << 8);
> +	return priv->cfg1_base + addroff;
> +}
> +
> +static void __iomem *cfg0_map(struct loongson_pci *priv, int bus,
> +				unsigned int devfn, int where)
> +{
> +	unsigned long addroff = 0x0;
> +
> +	if (bus != 0)
> +		addroff |= BIT(24); /* Type 1 Access */
> +	addroff |= (bus << 16) | (devfn << 8) | where;
> +	return priv->cfg0_base + addroff;
> +}
> +
> +void __iomem *pci_loongson_map_bus(struct pci_bus *bus, unsigned int devfn,
> +			       int where)
> +{
> +	unsigned char busnum = bus->number;
> +	struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
> +	struct loongson_pci *priv =  pci_host_bridge_priv(bridge);
> +
> +	/*
> +	 * Do not read more than one device on the bus other than
> +	 * the host bus. For our hardware the root bus is always bus 0.
> +	 */
> +	if (priv->flags & FLAG_DEV_FIX && busnum != 0 &&
> +		PCI_SLOT(devfn) > 0)
> +		return NULL;
> +
> +	/* CFG0 can only access standard space */
> +	if (where < PCI_CFG_SPACE_SIZE && priv->cfg0_base)
> +		return cfg0_map(priv, busnum, devfn, where);
> +
> +	/* CFG1 can access extended space */
> +	if (where < PCI_CFG_SPACE_EXP_SIZE && priv->cfg1_base)
> +		return cfg1_map(priv, busnum, devfn, where);
> +
> +	return NULL;
> +}
> +
> +static int loongson_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
> +{
> +	int irq;
> +	u8 val;
> +
> +	irq = of_irq_parse_and_map_pci(dev, slot, pin);
> +	if (irq > 0)
> +		return irq;
> +
> +	/* Care i8259 legacy systems */
> +	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &val);
> +	/* i8259 only have 15 IRQs */
> +	if (val > 15)
> +		return 0;
> +
> +	return val;
> +}
> +
> +/* H/w only accept 32-bit PCI operations */
> +static struct pci_ops loongson_pci_ops = {
> +	.map_bus = pci_loongson_map_bus,
> +	.read	= pci_generic_config_read32,
> +	.write	= pci_generic_config_write32,
> +};
> +
> +static const struct of_device_id loongson_pci_of_match[] = {
> +	{ .compatible = "loongson,ls2k-pci",
> +		.data = (void *)(FLAG_CFG0 | FLAG_CFG1 | FLAG_DEV_FIX), },
> +	{ .compatible = "loongson,ls7a-pci",
> +		.data = (void *)(FLAG_CFG0 | FLAG_CFG1 | FLAG_DEV_FIX), },
> +	{ .compatible = "loongson,rs780e-pci",
> +		.data = (void *)(FLAG_CFG0), },
> +	{}
> +};
> +
> +static int loongson_pci_probe(struct platform_device *pdev)
> +{
> +	struct loongson_pci *priv;
> +	struct device *dev = &pdev->dev;
> +	struct device_node *node = dev->of_node;
> +	struct pci_host_bridge *bridge;
> +	struct resource *regs;
> +	int err;
> +
> +	if (!node)
> +		return -ENODEV;
> +
> +	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*priv));
> +	if (!bridge)
> +		return -ENODEV;
> +
> +	priv = pci_host_bridge_priv(bridge);
> +	priv->pdev = pdev;
> +	priv->flags = (unsigned long)of_device_get_match_data(dev);
> +
> +	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	if (!regs) {
> +		dev_err(dev, "missing mem resources for cfg0\n");
> +		return -EINVAL;
> +	}
> +
> +	priv->cfg0_base = devm_pci_remap_cfg_resource(dev, regs);
> +	if (IS_ERR(priv->cfg0_base))
> +		return PTR_ERR(priv->cfg0_base);
> +
> +	/* CFG1 is optional */
> +	if (priv->flags & FLAG_CFG1) {
> +		regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> +		if (!regs)
> +			dev_info(dev, "missing mem resource for cfg1\n");
> +		else {
> +			priv->cfg1_base = devm_pci_remap_cfg_resource(dev, regs);
> +			if (IS_ERR(priv->cfg1_base))
> +				priv->cfg1_base = NULL;
> +		}
> +	}
> +
> +	err = pci_parse_request_of_pci_ranges(dev, &bridge->windows,
> +						&bridge->dma_ranges, NULL);
> +	if (err) {
> +		dev_err(dev, "failed to get bridge resources\n");
> +		return err;
> +	}
> +
> +	bridge->dev.parent = dev;
> +	bridge->sysdata = priv;
> +	bridge->ops = &loongson_pci_ops;
> +	bridge->map_irq = loongson_map_irq;
> +
> +	err = pci_host_probe(bridge);
> +	if (err)
> +		return err;
> +
> +	return 0;
> +}
> +
> +static struct platform_driver loongson_pci_driver = {
> +	.driver = {
> +		.name = "loongson-pci",
> +		.of_match_table = loongson_pci_of_match,
> +	},
> +	.probe = loongson_pci_probe,
> +};
> +builtin_platform_driver(loongson_pci_driver);
> -- 
> 2.26.2
> 

^ permalink raw reply	[flat|nested] 63+ messages in thread

* Re: [PATCH v10 5/5] MIPS: Loongson64: Switch to generic PCI driver
  2020-05-22 22:36         ` Thomas Bogendoerfer
@ 2020-05-26  9:12           ` Lorenzo Pieralisi
  2020-05-26  9:14             ` Jiaxun Yang
  2020-05-27 11:34             ` Thomas Bogendoerfer
  0 siblings, 2 replies; 63+ messages in thread
From: Lorenzo Pieralisi @ 2020-05-26  9:12 UTC (permalink / raw)
  To: Thomas Bogendoerfer
  Cc: Jiaxun Yang, linux-pci, Bjorn Helgaas, Rob Herring, Huacai Chen,
	Paul Burton, devicetree, linux-kernel, linux-mips

On Sat, May 23, 2020 at 12:36:56AM +0200, Thomas Bogendoerfer wrote:
> On Fri, May 22, 2020 at 04:22:11PM +0100, Lorenzo Pieralisi wrote:
> > On Fri, May 22, 2020 at 04:25:50PM +0200, Thomas Bogendoerfer wrote:
> > > On Thu, May 14, 2020 at 09:16:41PM +0800, Jiaxun Yang wrote:
> > > > We can now enable generic PCI driver in Kconfig, and remove legacy
> > > > PCI driver code.
> > > > 
> > > > Radeon vbios quirk is moved to the platform folder to fit the
> > > > new structure.
> > > > 
> > > > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> > > > --
> > > > v9: Fix licenses tag
> > > > ---
> > > >  arch/mips/Kconfig                  |   1 +
> > > >  arch/mips/loongson64/Makefile      |   2 +-
> > > >  arch/mips/loongson64/vbios_quirk.c |  29 ++++++++
> > > >  arch/mips/pci/Makefile             |   1 -
> > > >  arch/mips/pci/fixup-loongson3.c    |  71 ------------------
> > > >  arch/mips/pci/ops-loongson3.c      | 116 -----------------------------
> > > >  6 files changed, 31 insertions(+), 189 deletions(-)
> > > >  create mode 100644 arch/mips/loongson64/vbios_quirk.c
> > > >  delete mode 100644 arch/mips/pci/fixup-loongson3.c
> > > >  delete mode 100644 arch/mips/pci/ops-loongson3.c
> > > 
> > > Acked-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> > 
> > This patch (so the series) does not apply to v5.7-rc1 which is our
> > baseline. I reiterate the point, isn't it better to take the whole
> > series through the MIPS tree ?
> 
> sounds better then
> 
> > Failing that, the series has to
> > be rebased (or split differently so that it can be taken through
> > different trees), just let me know.
> 
> so let's take via mips-next. So can I add your Acked-by to the
> first three patches ?

I have acked patch 2, you have all required ACKs to get this series via
the MIPS tree now, apologies for the delay.

Thanks,
Lorenzo

^ permalink raw reply	[flat|nested] 63+ messages in thread

* Re: [PATCH v10 5/5] MIPS: Loongson64: Switch to generic PCI driver
  2020-05-26  9:12           ` Lorenzo Pieralisi
@ 2020-05-26  9:14             ` Jiaxun Yang
  2020-05-27 11:34             ` Thomas Bogendoerfer
  1 sibling, 0 replies; 63+ messages in thread
From: Jiaxun Yang @ 2020-05-26  9:14 UTC (permalink / raw)
  To: Lorenzo Pieralisi, Thomas Bogendoerfer
  Cc: linux-pci, Bjorn Helgaas, Rob Herring, Huacai Chen, Paul Burton,
	devicetree, linux-kernel, linux-mips



于 2020年5月26日 GMT+08:00 下午5:12:27, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> 写到:
>On Sat, May 23, 2020 at 12:36:56AM +0200, Thomas Bogendoerfer wrote:
>> On Fri, May 22, 2020 at 04:22:11PM +0100, Lorenzo Pieralisi wrote:
>> > On Fri, May 22, 2020 at 04:25:50PM +0200, Thomas Bogendoerfer wrote:
>> > > On Thu, May 14, 2020 at 09:16:41PM +0800, Jiaxun Yang wrote:
>> > > > We can now enable generic PCI driver in Kconfig, and remove legacy
>> > > > PCI driver code.
>> > > > 
>> > > > Radeon vbios quirk is moved to the platform folder to fit the
>> > > > new structure.
>> > > > 
>> > > > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>> > > > --
>> > > > v9: Fix licenses tag
>> > > > ---
>> > > >  arch/mips/Kconfig                  |   1 +
>> > > >  arch/mips/loongson64/Makefile      |   2 +-
>> > > >  arch/mips/loongson64/vbios_quirk.c |  29 ++++++++
>> > > >  arch/mips/pci/Makefile             |   1 -
>> > > >  arch/mips/pci/fixup-loongson3.c    |  71 ------------------
>> > > >  arch/mips/pci/ops-loongson3.c      | 116 -----------------------------
>> > > >  6 files changed, 31 insertions(+), 189 deletions(-)
>> > > >  create mode 100644 arch/mips/loongson64/vbios_quirk.c
>> > > >  delete mode 100644 arch/mips/pci/fixup-loongson3.c
>> > > >  delete mode 100644 arch/mips/pci/ops-loongson3.c
>> > > 
>> > > Acked-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
>> > 
>> > This patch (so the series) does not apply to v5.7-rc1 which is our
>> > baseline. I reiterate the point, isn't it better to take the whole
>> > series through the MIPS tree ?
>> 
>> sounds better then
>> 
>> > Failing that, the series has to
>> > be rebased (or split differently so that it can be taken through
>> > different trees), just let me know.
>> 
>> so let's take via mips-next. So can I add your Acked-by to the
>> first three patches ?
>
>I have acked patch 2, you have all required ACKs to get this series via
>the MIPS tree now, apologies for the delay.

I had received a regression report from test robot.

Will send v11 very soon.

Please take v11 into MIPS tree.

Thanks.


>
>Thanks,
>Lorenzo

-- 
Jiaxun Yang

^ permalink raw reply	[flat|nested] 63+ messages in thread

* [PATCH v11 0/5] Loongson Generic PCI v11
  2020-04-27  6:05 [PATCH v6 0/5] Loongson PCI Generic Driver Jiaxun Yang
                   ` (8 preceding siblings ...)
  2020-05-14 13:16 ` [PATCH v10 1/5] PCI: Don't disable decoding when mmio_always_on is set Jiaxun Yang
@ 2020-05-26  9:21 ` Jiaxun Yang
  2020-05-26  9:21   ` [PATCH v11 1/5] PCI: Don't disable decoding when mmio_always_on is set Jiaxun Yang
                     ` (5 more replies)
  9 siblings, 6 replies; 63+ messages in thread
From: Jiaxun Yang @ 2020-05-26  9:21 UTC (permalink / raw)
  To: linux-pci
  Cc: Jiaxun Yang, Bjorn Helgaas, Rob Herring, Thomas Bogendoerfer,
	Huacai Chen, Lorenzo Pieralisi, Paul Burton, devicetree,
	linux-kernel, linux-mips

v11 fixes a minor style issue in patch 2.

Now it have got enough ack,
Thomas, cloud you please apply it to mips-next?

Thanks.

Jiaxun Yang (5):
  PCI: Don't disable decoding when mmio_always_on is set
  PCI: Add Loongson PCI Controller support
  dt-bindings: Document Loongson PCI Host Controller
  MIPS: DTS: Loongson64: Add PCI Controller Node
  MIPS: Loongson64: Switch to generic PCI driver

 .../devicetree/bindings/pci/loongson.yaml     |  62 +++++
 arch/mips/Kconfig                             |   1 +
 arch/mips/boot/dts/loongson/rs780e-pch.dtsi   |  12 +
 arch/mips/loongson64/Makefile                 |   2 +-
 arch/mips/loongson64/vbios_quirk.c            |  29 ++
 arch/mips/pci/Makefile                        |   1 -
 arch/mips/pci/fixup-loongson3.c               |  71 -----
 arch/mips/pci/ops-loongson3.c                 | 116 --------
 drivers/pci/controller/Kconfig                |  10 +
 drivers/pci/controller/Makefile               |   1 +
 drivers/pci/controller/pci-loongson.c         | 247 ++++++++++++++++++
 drivers/pci/probe.c                           |   2 +-
 12 files changed, 364 insertions(+), 190 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pci/loongson.yaml
 create mode 100644 arch/mips/loongson64/vbios_quirk.c
 delete mode 100644 arch/mips/pci/fixup-loongson3.c
 delete mode 100644 arch/mips/pci/ops-loongson3.c
 create mode 100644 drivers/pci/controller/pci-loongson.c

-- 
2.27.0.rc0


^ permalink raw reply	[flat|nested] 63+ messages in thread

* [PATCH v11 1/5] PCI: Don't disable decoding when mmio_always_on is set
  2020-05-26  9:21 ` [PATCH v11 0/5] Loongson Generic PCI v11 Jiaxun Yang
@ 2020-05-26  9:21   ` Jiaxun Yang
  2020-05-26  9:21   ` [PATCH v11 2/5] PCI: Add Loongson PCI Controller support Jiaxun Yang
                     ` (4 subsequent siblings)
  5 siblings, 0 replies; 63+ messages in thread
From: Jiaxun Yang @ 2020-05-26  9:21 UTC (permalink / raw)
  To: linux-pci
  Cc: Jiaxun Yang, Bjorn Helgaas, Bjorn Helgaas, Rob Herring,
	Thomas Bogendoerfer, Huacai Chen, Lorenzo Pieralisi, Paul Burton,
	devicetree, linux-kernel, linux-mips

Don't disable MEM/IO decoding when a device have both non_compliant_bars
and mmio_always_on.

That would allow us quirk devices with junk in BARs but can't disable
their decoding.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Acked-by: Bjorn Helgaas <helgaas@kernel.org>
---
 drivers/pci/probe.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 77b8a145c39b..d9c2c3301a8a 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -1822,7 +1822,7 @@ int pci_setup_device(struct pci_dev *dev)
 	/* Device class may be changed after fixup */
 	class = dev->class >> 8;
 
-	if (dev->non_compliant_bars) {
+	if (dev->non_compliant_bars && !dev->mmio_always_on) {
 		pci_read_config_word(dev, PCI_COMMAND, &cmd);
 		if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
 			pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
-- 
2.27.0.rc0


^ permalink raw reply related	[flat|nested] 63+ messages in thread

* [PATCH v11 2/5] PCI: Add Loongson PCI Controller support
  2020-05-26  9:21 ` [PATCH v11 0/5] Loongson Generic PCI v11 Jiaxun Yang
  2020-05-26  9:21   ` [PATCH v11 1/5] PCI: Don't disable decoding when mmio_always_on is set Jiaxun Yang
@ 2020-05-26  9:21   ` Jiaxun Yang
  2020-05-26  9:21   ` [PATCH v11 3/5] dt-bindings: Document Loongson PCI Host Controller Jiaxun Yang
                     ` (3 subsequent siblings)
  5 siblings, 0 replies; 63+ messages in thread
From: Jiaxun Yang @ 2020-05-26  9:21 UTC (permalink / raw)
  To: linux-pci
  Cc: Jiaxun Yang, Rob Herring, Lorenzo Pieralisi, Bjorn Helgaas,
	Rob Herring, Thomas Bogendoerfer, Huacai Chen, Paul Burton,
	devicetree, linux-kernel, linux-mips

This controller can be found on Loongson-2K SoC, Loongson-3
systems with RS780E/LS7A PCH.

The RS780E part of code was previously located at
arch/mips/pci/ops-loongson3.c and now it can use generic PCI
driver implementation.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
--
v2:
	- Clean up according to rob's suggestions
	- Claim that it can't work as a module
v3:
	- Fix a typo
v4:
	- More clean-ups: Drop flag check, use devfn
v7:
	- Fix ordering according to huacai's suggestion
v8:
	- Style clean and bugfix according to Bjorn's review
v9:
	- Confirm with vendor about the details on system_bus BARs
	- Further cleanups
	- I think assume root_bus as 0 simplify our code a lot, as that's
		always valid to the hardware, as we're not ecam or dwc, we can't
		easily get host bus_nr via cfg, adding that will cause unnecessary
		overhead.

v10:
	- Enhance comments about system_bus quirk and host bus quirk.
v11:
	- Add static for pci_loongson_map_bus
---
 drivers/pci/controller/Kconfig        |  10 ++
 drivers/pci/controller/Makefile       |   1 +
 drivers/pci/controller/pci-loongson.c | 247 ++++++++++++++++++++++++++
 3 files changed, 258 insertions(+)
 create mode 100644 drivers/pci/controller/pci-loongson.c

diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 91bfdb784829..ae36edb1d7db 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -258,6 +258,16 @@ config PCI_HYPERV_INTERFACE
 	  The Hyper-V PCI Interface is a helper driver allows other drivers to
 	  have a common interface with the Hyper-V PCI frontend driver.
 
+config PCI_LOONGSON
+	bool "LOONGSON PCI Controller"
+	depends on MACH_LOONGSON64 || COMPILE_TEST
+	depends on OF
+	depends on PCI_QUIRKS
+	default MACH_LOONGSON64
+	help
+	  Say Y here if you want to enable PCI controller support on
+	  Loongson systems.
+
 source "drivers/pci/controller/dwc/Kconfig"
 source "drivers/pci/controller/mobiveil/Kconfig"
 source "drivers/pci/controller/cadence/Kconfig"
diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
index 158c59771824..fbac4b0190a0 100644
--- a/drivers/pci/controller/Makefile
+++ b/drivers/pci/controller/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
 obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
 obj-$(CONFIG_VMD) += vmd.o
 obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
+obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o
 # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
 obj-y				+= dwc/
 obj-y				+= mobiveil/
diff --git a/drivers/pci/controller/pci-loongson.c b/drivers/pci/controller/pci-loongson.c
new file mode 100644
index 000000000000..b590f3746ed2
--- /dev/null
+++ b/drivers/pci/controller/pci-loongson.c
@@ -0,0 +1,247 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Loongson PCI Host Controller Driver
+ *
+ * Copyright (C) 2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
+ */
+
+#include <linux/of_device.h>
+#include <linux/of_pci.h>
+#include <linux/pci.h>
+#include <linux/pci_ids.h>
+
+#include "../pci.h"
+
+/* Device IDs */
+#define DEV_PCIE_PORT_0	0x7a09
+#define DEV_PCIE_PORT_1	0x7a19
+#define DEV_PCIE_PORT_2	0x7a29
+
+#define DEV_LS2K_APB	0x7a02
+#define DEV_LS7A_CONF	0x7a10
+#define DEV_LS7A_LPC	0x7a0c
+
+#define FLAG_CFG0	BIT(0)
+#define FLAG_CFG1	BIT(1)
+#define FLAG_DEV_FIX	BIT(2)
+
+struct loongson_pci {
+	void __iomem *cfg0_base;
+	void __iomem *cfg1_base;
+	struct platform_device *pdev;
+	u32 flags;
+};
+
+/* Fixup wrong class code in PCIe bridges */
+static void bridge_class_quirk(struct pci_dev *dev)
+{
+	dev->class = PCI_CLASS_BRIDGE_PCI << 8;
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON,
+			DEV_PCIE_PORT_0, bridge_class_quirk);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON,
+			DEV_PCIE_PORT_1, bridge_class_quirk);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON,
+			DEV_PCIE_PORT_2, bridge_class_quirk);
+
+static void system_bus_quirk(struct pci_dev *pdev)
+{
+	/* 
+	 * The address space consumed by these devices is outside the
+	 * resources of the host bridge.
+	 */
+	pdev->mmio_always_on = 1;
+	pdev->non_compliant_bars = 1;
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
+			DEV_LS2K_APB, system_bus_quirk);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
+			DEV_LS7A_CONF, system_bus_quirk);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
+			DEV_LS7A_LPC, system_bus_quirk);
+
+static void loongson_mrrs_quirk(struct pci_dev *dev)
+{
+	struct pci_bus *bus = dev->bus;
+	struct pci_dev *bridge;
+	static const struct pci_device_id bridge_devids[] = {
+		{ PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_0) },
+		{ PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_1) },
+		{ PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_2) },
+		{ 0, },
+	};
+
+	/* look for the matching bridge */
+	while (!pci_is_root_bus(bus)) {
+		bridge = bus->self;
+		bus = bus->parent;
+		/*
+		 * Some Loongson PCIe ports have a h/w limitation of
+		 * 256 bytes maximum read request size. They can't handle
+		 * anything larger than this. So force this limit on
+		 * any devices attached under these ports.
+		 */
+		if (pci_match_id(bridge_devids, bridge)) {
+			if (pcie_get_readrq(dev) > 256) {
+				pci_info(dev, "limiting MRRS to 256\n");
+				pcie_set_readrq(dev, 256);
+			}
+			break;
+		}
+	}
+}
+DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, loongson_mrrs_quirk);
+
+static void __iomem *cfg1_map(struct loongson_pci *priv, int bus,
+				unsigned int devfn, int where)
+{
+	unsigned long addroff = 0x0;
+
+	if (bus != 0)
+		addroff |= BIT(28); /* Type 1 Access */
+	addroff |= (where & 0xff) | ((where & 0xf00) << 16);
+	addroff |= (bus << 16) | (devfn << 8);
+	return priv->cfg1_base + addroff;
+}
+
+static void __iomem *cfg0_map(struct loongson_pci *priv, int bus,
+				unsigned int devfn, int where)
+{
+	unsigned long addroff = 0x0;
+
+	if (bus != 0)
+		addroff |= BIT(24); /* Type 1 Access */
+	addroff |= (bus << 16) | (devfn << 8) | where;
+	return priv->cfg0_base + addroff;
+}
+
+static void __iomem *pci_loongson_map_bus(struct pci_bus *bus, unsigned int devfn,
+			       int where)
+{
+	unsigned char busnum = bus->number;
+	struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
+	struct loongson_pci *priv =  pci_host_bridge_priv(bridge);
+
+	/*
+	 * Do not read more than one device on the bus other than
+	 * the host bus. For our hardware the root bus is always bus 0.
+	 */
+	if (priv->flags & FLAG_DEV_FIX && busnum != 0 &&
+		PCI_SLOT(devfn) > 0)
+		return NULL;
+
+	/* CFG0 can only access standard space */
+	if (where < PCI_CFG_SPACE_SIZE && priv->cfg0_base)
+		return cfg0_map(priv, busnum, devfn, where);
+
+	/* CFG1 can access extended space */
+	if (where < PCI_CFG_SPACE_EXP_SIZE && priv->cfg1_base)
+		return cfg1_map(priv, busnum, devfn, where);
+
+	return NULL;
+}
+
+static int loongson_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+	int irq;
+	u8 val;
+
+	irq = of_irq_parse_and_map_pci(dev, slot, pin);
+	if (irq > 0)
+		return irq;
+
+	/* Care i8259 legacy systems */
+	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &val);
+	/* i8259 only have 15 IRQs */
+	if (val > 15)
+		return 0;
+
+	return val;
+}
+
+/* H/w only accept 32-bit PCI operations */
+static struct pci_ops loongson_pci_ops = {
+	.map_bus = pci_loongson_map_bus,
+	.read	= pci_generic_config_read32,
+	.write	= pci_generic_config_write32,
+};
+
+static const struct of_device_id loongson_pci_of_match[] = {
+	{ .compatible = "loongson,ls2k-pci",
+		.data = (void *)(FLAG_CFG0 | FLAG_CFG1 | FLAG_DEV_FIX), },
+	{ .compatible = "loongson,ls7a-pci",
+		.data = (void *)(FLAG_CFG0 | FLAG_CFG1 | FLAG_DEV_FIX), },
+	{ .compatible = "loongson,rs780e-pci",
+		.data = (void *)(FLAG_CFG0), },
+	{}
+};
+
+static int loongson_pci_probe(struct platform_device *pdev)
+{
+	struct loongson_pci *priv;
+	struct device *dev = &pdev->dev;
+	struct device_node *node = dev->of_node;
+	struct pci_host_bridge *bridge;
+	struct resource *regs;
+	int err;
+
+	if (!node)
+		return -ENODEV;
+
+	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*priv));
+	if (!bridge)
+		return -ENODEV;
+
+	priv = pci_host_bridge_priv(bridge);
+	priv->pdev = pdev;
+	priv->flags = (unsigned long)of_device_get_match_data(dev);
+
+	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!regs) {
+		dev_err(dev, "missing mem resources for cfg0\n");
+		return -EINVAL;
+	}
+
+	priv->cfg0_base = devm_pci_remap_cfg_resource(dev, regs);
+	if (IS_ERR(priv->cfg0_base))
+		return PTR_ERR(priv->cfg0_base);
+
+	/* CFG1 is optional */
+	if (priv->flags & FLAG_CFG1) {
+		regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+		if (!regs)
+			dev_info(dev, "missing mem resource for cfg1\n");
+		else {
+			priv->cfg1_base = devm_pci_remap_cfg_resource(dev, regs);
+			if (IS_ERR(priv->cfg1_base))
+				priv->cfg1_base = NULL;
+		}
+	}
+
+	err = pci_parse_request_of_pci_ranges(dev, &bridge->windows,
+						&bridge->dma_ranges, NULL);
+	if (err) {
+		dev_err(dev, "failed to get bridge resources\n");
+		return err;
+	}
+
+	bridge->dev.parent = dev;
+	bridge->sysdata = priv;
+	bridge->ops = &loongson_pci_ops;
+	bridge->map_irq = loongson_map_irq;
+
+	err = pci_host_probe(bridge);
+	if (err)
+		return err;
+
+	return 0;
+}
+
+static struct platform_driver loongson_pci_driver = {
+	.driver = {
+		.name = "loongson-pci",
+		.of_match_table = loongson_pci_of_match,
+	},
+	.probe = loongson_pci_probe,
+};
+builtin_platform_driver(loongson_pci_driver);
-- 
2.27.0.rc0


^ permalink raw reply related	[flat|nested] 63+ messages in thread

* [PATCH v11 3/5] dt-bindings: Document Loongson PCI Host Controller
  2020-05-26  9:21 ` [PATCH v11 0/5] Loongson Generic PCI v11 Jiaxun Yang
  2020-05-26  9:21   ` [PATCH v11 1/5] PCI: Don't disable decoding when mmio_always_on is set Jiaxun Yang
  2020-05-26  9:21   ` [PATCH v11 2/5] PCI: Add Loongson PCI Controller support Jiaxun Yang
@ 2020-05-26  9:21   ` Jiaxun Yang
  2020-05-26  9:21   ` [PATCH v11 4/5] MIPS: DTS: Loongson64: Add PCI Controller Node Jiaxun Yang
                     ` (2 subsequent siblings)
  5 siblings, 0 replies; 63+ messages in thread
From: Jiaxun Yang @ 2020-05-26  9:21 UTC (permalink / raw)
  To: linux-pci
  Cc: Jiaxun Yang, Rob Herring, Bjorn Helgaas, Rob Herring,
	Thomas Bogendoerfer, Huacai Chen, Lorenzo Pieralisi, Paul Burton,
	devicetree, linux-kernel, linux-mips

PCI host controller found on Loongson PCHs and SoCs.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../devicetree/bindings/pci/loongson.yaml     | 62 +++++++++++++++++++
 1 file changed, 62 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/loongson.yaml

diff --git a/Documentation/devicetree/bindings/pci/loongson.yaml b/Documentation/devicetree/bindings/pci/loongson.yaml
new file mode 100644
index 000000000000..30e7cf1aeb87
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/loongson.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/loongson.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Loongson PCI Host Controller
+
+maintainers:
+  - Jiaxun Yang <jiaxun.yang@flygoat.com>
+
+description: |+
+  PCI host controller found on Loongson PCHs and SoCs.
+
+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+  compatible:
+    oneOf:
+      - const: loongson,ls2k-pci
+      - const: loongson,ls7a-pci
+      - const: loongson,rs780e-pci
+
+  reg:
+    minItems: 1
+    maxItems: 2
+    items:
+      - description: CFG0 standard config space register
+      - description: CFG1 extended config space register
+
+  ranges:
+    minItems: 1
+    maxItems: 3
+
+
+required:
+  - compatible
+  - reg
+  - ranges
+
+examples:
+  - |
+
+    bus {
+        #address-cells = <2>;
+        #size-cells = <2>;
+        pcie@1a000000 {
+            compatible = "loongson,rs780e-pci";
+            device_type = "pci";
+            #address-cells = <3>;
+            #size-cells = <2>;
+
+            // CPU_PHYSICAL(2)  SIZE(2)
+            reg = <0x0 0x1a000000  0x0 0x2000000>;
+
+            // BUS_ADDRESS(3)  CPU_PHYSICAL(2)  SIZE(2)
+            ranges = <0x01000000 0x0 0x00004000  0x0 0x00004000  0x0 0x00004000>,
+                     <0x02000000 0x0 0x40000000  0x0 0x40000000  0x0 0x40000000>;
+        };
+    };
+...
-- 
2.27.0.rc0


^ permalink raw reply related	[flat|nested] 63+ messages in thread

* [PATCH v11 4/5] MIPS: DTS: Loongson64: Add PCI Controller Node
  2020-05-26  9:21 ` [PATCH v11 0/5] Loongson Generic PCI v11 Jiaxun Yang
                     ` (2 preceding siblings ...)
  2020-05-26  9:21   ` [PATCH v11 3/5] dt-bindings: Document Loongson PCI Host Controller Jiaxun Yang
@ 2020-05-26  9:21   ` Jiaxun Yang
  2020-05-26  9:21   ` [PATCH v11 5/5] MIPS: Loongson64: Switch to generic PCI driver Jiaxun Yang
  2020-05-27 11:35   ` [PATCH v11 0/5] Loongson Generic PCI v11 Thomas Bogendoerfer
  5 siblings, 0 replies; 63+ messages in thread
From: Jiaxun Yang @ 2020-05-26  9:21 UTC (permalink / raw)
  To: linux-pci
  Cc: Jiaxun Yang, Bjorn Helgaas, Rob Herring, Thomas Bogendoerfer,
	Huacai Chen, Lorenzo Pieralisi, Paul Burton, devicetree,
	linux-kernel, linux-mips

Add PCI Host controller node for Loongson64 with RS780E PCH dts.
Note that PCI interrupts are probed via legacy way, as different
machine have different interrupt arrangement, we can't cover all
of them in dt.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 arch/mips/boot/dts/loongson/rs780e-pch.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/mips/boot/dts/loongson/rs780e-pch.dtsi b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
index 8687c4f7370a..d0d5d60a8697 100644
--- a/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
+++ b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
@@ -9,6 +9,18 @@ bus@10000000 {
 				0 0x40000000 0 0x40000000 0 0x40000000
 				0xfd 0xfe000000 0xfd 0xfe000000  0 0x2000000 /* PCI Config Space */>;
 
+		pci@1a000000 {
+			compatible = "loongson,rs780e-pci";
+			device_type = "pci";
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			reg = <0 0x1a000000 0 0x02000000>;
+
+			ranges = <0x01000000 0 0x00004000 0 0x18004000 0 0x00004000>,
+				 <0x02000000 0 0x40000000 0 0x40000000 0 0x40000000>;
+		};
+
 		isa {
 			compatible = "isa";
 			#address-cells = <2>;
-- 
2.27.0.rc0


^ permalink raw reply related	[flat|nested] 63+ messages in thread

* [PATCH v11 5/5] MIPS: Loongson64: Switch to generic PCI driver
  2020-05-26  9:21 ` [PATCH v11 0/5] Loongson Generic PCI v11 Jiaxun Yang
                     ` (3 preceding siblings ...)
  2020-05-26  9:21   ` [PATCH v11 4/5] MIPS: DTS: Loongson64: Add PCI Controller Node Jiaxun Yang
@ 2020-05-26  9:21   ` Jiaxun Yang
  2020-05-27 11:35   ` [PATCH v11 0/5] Loongson Generic PCI v11 Thomas Bogendoerfer
  5 siblings, 0 replies; 63+ messages in thread
From: Jiaxun Yang @ 2020-05-26  9:21 UTC (permalink / raw)
  To: linux-pci
  Cc: Jiaxun Yang, Bjorn Helgaas, Rob Herring, Thomas Bogendoerfer,
	Huacai Chen, Lorenzo Pieralisi, Paul Burton, devicetree,
	linux-kernel, linux-mips

We can now enable generic PCI driver in Kconfig, and remove legacy
PCI driver code.

Radeon vbios quirk is moved to the platform folder to fit the
new structure.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
--
v9: Fix licenses tag
---
 arch/mips/Kconfig                  |   1 +
 arch/mips/loongson64/Makefile      |   2 +-
 arch/mips/loongson64/vbios_quirk.c |  29 ++++++++
 arch/mips/pci/Makefile             |   1 -
 arch/mips/pci/fixup-loongson3.c    |  71 ------------------
 arch/mips/pci/ops-loongson3.c      | 116 -----------------------------
 6 files changed, 31 insertions(+), 189 deletions(-)
 create mode 100644 arch/mips/loongson64/vbios_quirk.c
 delete mode 100644 arch/mips/pci/fixup-loongson3.c
 delete mode 100644 arch/mips/pci/ops-loongson3.c

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 0519ca9f00f9..7a4fcc4ade1f 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -480,6 +480,7 @@ config MACH_LOONGSON64
 	select IRQ_MIPS_CPU
 	select NR_CPUS_DEFAULT_64
 	select USE_GENERIC_EARLY_PRINTK_8250
+	select PCI_DRIVERS_GENERIC
 	select SYS_HAS_CPU_LOONGSON64
 	select SYS_HAS_EARLY_PRINTK
 	select SYS_SUPPORTS_SMP
diff --git a/arch/mips/loongson64/Makefile b/arch/mips/loongson64/Makefile
index 6f3c2b47f66f..6f81b822aeae 100644
--- a/arch/mips/loongson64/Makefile
+++ b/arch/mips/loongson64/Makefile
@@ -8,5 +8,5 @@ obj-$(CONFIG_MACH_LOONGSON64) += cop2-ex.o platform.o dma.o \
 obj-$(CONFIG_SMP)	+= smp.o
 obj-$(CONFIG_NUMA)	+= numa.o
 obj-$(CONFIG_RS780_HPET) += hpet.o
-obj-$(CONFIG_PCI) += pci.o
 obj-$(CONFIG_SUSPEND) += pm.o
+obj-$(CONFIG_PCI_QUIRKS) += vbios_quirk.o
diff --git a/arch/mips/loongson64/vbios_quirk.c b/arch/mips/loongson64/vbios_quirk.c
new file mode 100644
index 000000000000..9a29e94d3db1
--- /dev/null
+++ b/arch/mips/loongson64/vbios_quirk.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <linux/pci.h>
+#include <loongson.h>
+
+static void pci_fixup_radeon(struct pci_dev *pdev)
+{
+	struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
+
+	if (res->start)
+		return;
+
+	if (!loongson_sysconf.vgabios_addr)
+		return;
+
+	pci_disable_rom(pdev);
+	if (res->parent)
+		release_resource(res);
+
+	res->start = virt_to_phys((void *) loongson_sysconf.vgabios_addr);
+	res->end   = res->start + 256*1024 - 1;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ROM_SHADOW |
+		     IORESOURCE_PCI_FIXED;
+
+	dev_info(&pdev->dev, "BAR %d: assigned %pR for Radeon ROM\n",
+		 PCI_ROM_RESOURCE, res);
+}
+DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, 0x9615,
+				PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_radeon);
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 342ce10ef593..438f10955d89 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -35,7 +35,6 @@ obj-$(CONFIG_LASAT)		+= pci-lasat.o
 obj-$(CONFIG_MIPS_COBALT)	+= fixup-cobalt.o
 obj-$(CONFIG_LEMOTE_FULOONG2E)	+= fixup-fuloong2e.o ops-loongson2.o
 obj-$(CONFIG_LEMOTE_MACH2F)	+= fixup-lemote2f.o ops-loongson2.o
-obj-$(CONFIG_MACH_LOONGSON64)	+= fixup-loongson3.o ops-loongson3.o
 obj-$(CONFIG_MIPS_MALTA)	+= fixup-malta.o pci-malta.o
 obj-$(CONFIG_PMC_MSP7120_GW)	+= fixup-pmcmsp.o ops-pmcmsp.o
 obj-$(CONFIG_PMC_MSP7120_EVAL)	+= fixup-pmcmsp.o ops-pmcmsp.o
diff --git a/arch/mips/pci/fixup-loongson3.c b/arch/mips/pci/fixup-loongson3.c
deleted file mode 100644
index 8a741c2c6685..000000000000
--- a/arch/mips/pci/fixup-loongson3.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * fixup-loongson3.c
- *
- * Copyright (C) 2012 Lemote, Inc.
- * Author: Xiang Yu, xiangy@lemote.com
- *         Chen Huacai, chenhc@lemote.com
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- * THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- * WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- * NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- * USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-
-#include <linux/pci.h>
-#include <boot_param.h>
-
-static void print_fixup_info(const struct pci_dev *pdev)
-{
-	dev_info(&pdev->dev, "Device %x:%x, irq %d\n",
-			pdev->vendor, pdev->device, pdev->irq);
-}
-
-int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
-	print_fixup_info(dev);
-	return dev->irq;
-}
-
-static void pci_fixup_radeon(struct pci_dev *pdev)
-{
-	struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
-
-	if (res->start)
-		return;
-
-	if (!loongson_sysconf.vgabios_addr)
-		return;
-
-	pci_disable_rom(pdev);
-	if (res->parent)
-		release_resource(res);
-
-	res->start = virt_to_phys((void *) loongson_sysconf.vgabios_addr);
-	res->end   = res->start + 256*1024 - 1;
-	res->flags = IORESOURCE_MEM | IORESOURCE_ROM_SHADOW |
-		     IORESOURCE_PCI_FIXED;
-
-	dev_info(&pdev->dev, "BAR %d: assigned %pR for Radeon ROM\n",
-		 PCI_ROM_RESOURCE, res);
-}
-
-DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
-				PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_radeon);
-
-/* Do platform specific device initialization at pci_enable_device() time */
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
-	return 0;
-}
diff --git a/arch/mips/pci/ops-loongson3.c b/arch/mips/pci/ops-loongson3.c
deleted file mode 100644
index 2f6ad36bdea6..000000000000
--- a/arch/mips/pci/ops-loongson3.c
+++ /dev/null
@@ -1,116 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-
-#include <asm/mips-boards/bonito64.h>
-
-#include <loongson.h>
-
-#define PCI_ACCESS_READ  0
-#define PCI_ACCESS_WRITE 1
-
-#define HT1LO_PCICFG_BASE      0x1a000000
-#define HT1LO_PCICFG_BASE_TP1  0x1b000000
-
-static int loongson3_pci_config_access(unsigned char access_type,
-		struct pci_bus *bus, unsigned int devfn,
-		int where, u32 *data)
-{
-	unsigned char busnum = bus->number;
-	int function = PCI_FUNC(devfn);
-	int device = PCI_SLOT(devfn);
-	int reg = where & ~3;
-	void *addrp;
-	u64 addr;
-
-	if (where < PCI_CFG_SPACE_SIZE) { /* standard config */
-		addr = (busnum << 16) | (device << 11) | (function << 8) | reg;
-		if (busnum == 0) {
-			if (device > 31)
-				return PCIBIOS_DEVICE_NOT_FOUND;
-			addrp = (void *)TO_UNCAC(HT1LO_PCICFG_BASE | addr);
-		} else {
-			addrp = (void *)TO_UNCAC(HT1LO_PCICFG_BASE_TP1 | addr);
-		}
-	} else if (where < PCI_CFG_SPACE_EXP_SIZE) {  /* extended config */
-		struct pci_dev *rootdev;
-
-		rootdev = pci_get_domain_bus_and_slot(0, 0, 0);
-		if (!rootdev)
-			return PCIBIOS_DEVICE_NOT_FOUND;
-
-		addr = pci_resource_start(rootdev, 3);
-		if (!addr)
-			return PCIBIOS_DEVICE_NOT_FOUND;
-
-		addr |= busnum << 20 | device << 15 | function << 12 | reg;
-		addrp = (void *)TO_UNCAC(addr);
-	} else {
-		return PCIBIOS_DEVICE_NOT_FOUND;
-	}
-
-	if (access_type == PCI_ACCESS_WRITE)
-		writel(*data, addrp);
-	else {
-		*data = readl(addrp);
-		if (*data == 0xffffffff) {
-			*data = -1;
-			return PCIBIOS_DEVICE_NOT_FOUND;
-		}
-	}
-	return PCIBIOS_SUCCESSFUL;
-}
-
-static int loongson3_pci_pcibios_read(struct pci_bus *bus, unsigned int devfn,
-				 int where, int size, u32 *val)
-{
-	u32 data = 0;
-	int ret = loongson3_pci_config_access(PCI_ACCESS_READ,
-			bus, devfn, where, &data);
-
-	if (ret != PCIBIOS_SUCCESSFUL)
-		return ret;
-
-	if (size == 1)
-		*val = (data >> ((where & 3) << 3)) & 0xff;
-	else if (size == 2)
-		*val = (data >> ((where & 3) << 3)) & 0xffff;
-	else
-		*val = data;
-
-	return PCIBIOS_SUCCESSFUL;
-}
-
-static int loongson3_pci_pcibios_write(struct pci_bus *bus, unsigned int devfn,
-				  int where, int size, u32 val)
-{
-	u32 data = 0;
-	int ret;
-
-	if (size == 4)
-		data = val;
-	else {
-		ret = loongson3_pci_config_access(PCI_ACCESS_READ,
-				bus, devfn, where, &data);
-		if (ret != PCIBIOS_SUCCESSFUL)
-			return ret;
-
-		if (size == 1)
-			data = (data & ~(0xff << ((where & 3) << 3))) |
-			    (val << ((where & 3) << 3));
-		else if (size == 2)
-			data = (data & ~(0xffff << ((where & 3) << 3))) |
-			    (val << ((where & 3) << 3));
-	}
-
-	ret = loongson3_pci_config_access(PCI_ACCESS_WRITE,
-			bus, devfn, where, &data);
-
-	return ret;
-}
-
-struct pci_ops loongson_pci_ops = {
-	.read = loongson3_pci_pcibios_read,
-	.write = loongson3_pci_pcibios_write
-};
-- 
2.27.0.rc0


^ permalink raw reply related	[flat|nested] 63+ messages in thread

* Re: [PATCH v10 5/5] MIPS: Loongson64: Switch to generic PCI driver
  2020-05-26  9:12           ` Lorenzo Pieralisi
  2020-05-26  9:14             ` Jiaxun Yang
@ 2020-05-27 11:34             ` Thomas Bogendoerfer
  1 sibling, 0 replies; 63+ messages in thread
From: Thomas Bogendoerfer @ 2020-05-27 11:34 UTC (permalink / raw)
  To: Lorenzo Pieralisi
  Cc: Jiaxun Yang, linux-pci, Bjorn Helgaas, Rob Herring, Huacai Chen,
	Paul Burton, devicetree, linux-kernel, linux-mips

On Tue, May 26, 2020 at 10:12:27AM +0100, Lorenzo Pieralisi wrote:
> On Sat, May 23, 2020 at 12:36:56AM +0200, Thomas Bogendoerfer wrote:
> > On Fri, May 22, 2020 at 04:22:11PM +0100, Lorenzo Pieralisi wrote:
> > > On Fri, May 22, 2020 at 04:25:50PM +0200, Thomas Bogendoerfer wrote:
> > > > On Thu, May 14, 2020 at 09:16:41PM +0800, Jiaxun Yang wrote:
> > > > > We can now enable generic PCI driver in Kconfig, and remove legacy
> > > > > PCI driver code.
> > > > > 
> > > > > Radeon vbios quirk is moved to the platform folder to fit the
> > > > > new structure.
> > > > > 
> > > > > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> > > > > --
> > > > > v9: Fix licenses tag
> > > > > ---
> > > > >  arch/mips/Kconfig                  |   1 +
> > > > >  arch/mips/loongson64/Makefile      |   2 +-
> > > > >  arch/mips/loongson64/vbios_quirk.c |  29 ++++++++
> > > > >  arch/mips/pci/Makefile             |   1 -
> > > > >  arch/mips/pci/fixup-loongson3.c    |  71 ------------------
> > > > >  arch/mips/pci/ops-loongson3.c      | 116 -----------------------------
> > > > >  6 files changed, 31 insertions(+), 189 deletions(-)
> > > > >  create mode 100644 arch/mips/loongson64/vbios_quirk.c
> > > > >  delete mode 100644 arch/mips/pci/fixup-loongson3.c
> > > > >  delete mode 100644 arch/mips/pci/ops-loongson3.c
> > > > 
> > > > Acked-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> > > 
> > > This patch (so the series) does not apply to v5.7-rc1 which is our
> > > baseline. I reiterate the point, isn't it better to take the whole
> > > series through the MIPS tree ?
> > 
> > sounds better then
> > 
> > > Failing that, the series has to
> > > be rebased (or split differently so that it can be taken through
> > > different trees), just let me know.
> > 
> > so let's take via mips-next. So can I add your Acked-by to the
> > first three patches ?
> 
> I have acked patch 2, you have all required ACKs to get this series via
> the MIPS tree now, apologies for the delay.

perfect, thanks.

Thomas.


-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

^ permalink raw reply	[flat|nested] 63+ messages in thread

* Re: [PATCH v11 0/5] Loongson Generic PCI v11
  2020-05-26  9:21 ` [PATCH v11 0/5] Loongson Generic PCI v11 Jiaxun Yang
                     ` (4 preceding siblings ...)
  2020-05-26  9:21   ` [PATCH v11 5/5] MIPS: Loongson64: Switch to generic PCI driver Jiaxun Yang
@ 2020-05-27 11:35   ` Thomas Bogendoerfer
  5 siblings, 0 replies; 63+ messages in thread
From: Thomas Bogendoerfer @ 2020-05-27 11:35 UTC (permalink / raw)
  To: Jiaxun Yang
  Cc: linux-pci, Bjorn Helgaas, Rob Herring, Huacai Chen,
	Lorenzo Pieralisi, Paul Burton, devicetree, linux-kernel,
	linux-mips

On Tue, May 26, 2020 at 05:21:11PM +0800, Jiaxun Yang wrote:
> v11 fixes a minor style issue in patch 2.
> 
> Now it have got enough ack,
> Thomas, cloud you please apply it to mips-next?
> 
> Thanks.
> 
> Jiaxun Yang (5):
>   PCI: Don't disable decoding when mmio_always_on is set
>   PCI: Add Loongson PCI Controller support
>   dt-bindings: Document Loongson PCI Host Controller
>   MIPS: DTS: Loongson64: Add PCI Controller Node
>   MIPS: Loongson64: Switch to generic PCI driver
> 
>  .../devicetree/bindings/pci/loongson.yaml     |  62 +++++
>  arch/mips/Kconfig                             |   1 +
>  arch/mips/boot/dts/loongson/rs780e-pch.dtsi   |  12 +
>  arch/mips/loongson64/Makefile                 |   2 +-
>  arch/mips/loongson64/vbios_quirk.c            |  29 ++
>  arch/mips/pci/Makefile                        |   1 -
>  arch/mips/pci/fixup-loongson3.c               |  71 -----
>  arch/mips/pci/ops-loongson3.c                 | 116 --------
>  drivers/pci/controller/Kconfig                |  10 +
>  drivers/pci/controller/Makefile               |   1 +
>  drivers/pci/controller/pci-loongson.c         | 247 ++++++++++++++++++
>  drivers/pci/probe.c                           |   2 +-
>  12 files changed, 364 insertions(+), 190 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/pci/loongson.yaml
>  create mode 100644 arch/mips/loongson64/vbios_quirk.c
>  delete mode 100644 arch/mips/pci/fixup-loongson3.c
>  delete mode 100644 arch/mips/pci/ops-loongson3.c
>  create mode 100644 drivers/pci/controller/pci-loongson.c

applied to mips-next.

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

^ permalink raw reply	[flat|nested] 63+ messages in thread

end of thread, other threads:[~2020-05-27 11:39 UTC | newest]

Thread overview: 63+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-04-27  6:05 [PATCH v6 0/5] Loongson PCI Generic Driver Jiaxun Yang
2020-04-27  6:05 ` [PATCH v6 1/5] PCI: Don't disable decoding when mmio_always_on is set Jiaxun Yang
2020-04-27  7:42   ` Philippe Mathieu-Daudé
2020-04-27  6:05 ` [PATCH v6 2/5] PCI: Add Loongson PCI Controller support Jiaxun Yang
2020-04-27  6:29   ` Huacai Chen
2020-04-27  6:46     ` Jiaxun Yang
2020-04-27  6:05 ` [PATCH v6 3/5] dt-bindings: Document Loongson PCI Host Controller Jiaxun Yang
2020-04-27  6:05 ` [PATCH v6 4/5] MIPS: DTS: Loongson64: Add PCI Controller Node Jiaxun Yang
2020-04-27  6:05 ` [PATCH v6 5/5] MIPS: Loongson64: Switch to generic PCI driver Jiaxun Yang
2020-04-28  1:14 ` [PATCH v7 0/5] Loongson PCI Generic Driver Jiaxun Yang
2020-04-28  1:14   ` [PATCH v7 1/5] PCI: Don't disable decoding when mmio_always_on is set Jiaxun Yang
2020-05-08 18:51     ` Bjorn Helgaas
2020-05-20 20:55     ` Rob Herring
2020-04-28  1:14   ` [PATCH v7 2/5] PCI: Add Loongson PCI Controller support Jiaxun Yang
2020-04-29 18:43     ` Rob Herring
2020-05-04 23:43     ` Bjorn Helgaas
2020-05-06  6:08       ` Jiaxun Yang
2020-04-28  1:14   ` [PATCH v7 3/5] dt-bindings: Document Loongson PCI Host Controller Jiaxun Yang
2020-04-28  1:14   ` [PATCH v7 4/5] MIPS: DTS: Loongson64: Add PCI Controller Node Jiaxun Yang
2020-04-28  1:14   ` [PATCH v7 5/5] MIPS: Loongson64: Switch to generic PCI driver Jiaxun Yang
2020-05-08 11:34 ` [PATCH v8 1/5] PCI: Don't disable decoding when mmio_always_on is set Jiaxun Yang
2020-05-08 11:34   ` [PATCH v8 2/5] PCI: Add Loongson PCI Controller support Jiaxun Yang
2020-05-08 17:17     ` Bjorn Helgaas
2020-05-08 17:28       ` Jiaxun Yang
2020-05-08 19:34         ` Bjorn Helgaas
2020-05-08 11:34   ` [PATCH v8 3/5] dt-bindings: Document Loongson PCI Host Controller Jiaxun Yang
2020-05-08 11:34   ` [PATCH v8 4/5] MIPS: DTS: Loongson64: Add PCI Controller Node Jiaxun Yang
2020-05-08 11:34   ` [PATCH v8 5/5] MIPS: Loongson64: Switch to generic PCI driver Jiaxun Yang
2020-05-08 22:04     ` Bjorn Helgaas
2020-05-12  7:43 ` [PATCH v9 1/5] PCI: Don't disable decoding when mmio_always_on is set Jiaxun Yang
2020-05-12  7:43   ` [PATCH v9 2/5] PCI: Add Loongson PCI Controller support Jiaxun Yang
2020-05-12 18:06     ` Bjorn Helgaas
2020-05-13  1:20       ` Jiaxun Yang
2020-05-13 15:05         ` Bjorn Helgaas
2020-05-12  7:43   ` [PATCH v9 3/5] dt-bindings: Document Loongson PCI Host Controller Jiaxun Yang
2020-05-12  7:43   ` [PATCH v9 4/5] MIPS: DTS: Loongson64: Add PCI Controller Node Jiaxun Yang
2020-05-12  7:43   ` [PATCH v9 5/5] MIPS: Loongson64: Switch to generic PCI driver Jiaxun Yang
2020-05-14 13:16 ` [PATCH v10 1/5] PCI: Don't disable decoding when mmio_always_on is set Jiaxun Yang
2020-05-14 13:16   ` [PATCH v10 2/5] PCI: Add Loongson PCI Controller support Jiaxun Yang
2020-05-20 11:57     ` Jiaxun Yang
2020-05-22 13:10       ` Lorenzo Pieralisi
2020-05-22 13:32         ` Jiaxun Yang
2020-05-22 13:40           ` Lorenzo Pieralisi
2020-05-22 14:27             ` Thomas Bogendoerfer
2020-05-22 14:27           ` Thomas Bogendoerfer
2020-05-26  9:10     ` Lorenzo Pieralisi
2020-05-14 13:16   ` [PATCH v10 3/5] dt-bindings: Document Loongson PCI Host Controller Jiaxun Yang
2020-05-14 13:16   ` [PATCH v10 4/5] MIPS: DTS: Loongson64: Add PCI Controller Node Jiaxun Yang
2020-05-22 14:25     ` Thomas Bogendoerfer
2020-05-14 13:16   ` [PATCH v10 5/5] MIPS: Loongson64: Switch to generic PCI driver Jiaxun Yang
2020-05-22 14:25     ` Thomas Bogendoerfer
2020-05-22 15:22       ` Lorenzo Pieralisi
2020-05-22 22:36         ` Thomas Bogendoerfer
2020-05-26  9:12           ` Lorenzo Pieralisi
2020-05-26  9:14             ` Jiaxun Yang
2020-05-27 11:34             ` Thomas Bogendoerfer
2020-05-26  9:21 ` [PATCH v11 0/5] Loongson Generic PCI v11 Jiaxun Yang
2020-05-26  9:21   ` [PATCH v11 1/5] PCI: Don't disable decoding when mmio_always_on is set Jiaxun Yang
2020-05-26  9:21   ` [PATCH v11 2/5] PCI: Add Loongson PCI Controller support Jiaxun Yang
2020-05-26  9:21   ` [PATCH v11 3/5] dt-bindings: Document Loongson PCI Host Controller Jiaxun Yang
2020-05-26  9:21   ` [PATCH v11 4/5] MIPS: DTS: Loongson64: Add PCI Controller Node Jiaxun Yang
2020-05-26  9:21   ` [PATCH v11 5/5] MIPS: Loongson64: Switch to generic PCI driver Jiaxun Yang
2020-05-27 11:35   ` [PATCH v11 0/5] Loongson Generic PCI v11 Thomas Bogendoerfer

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