From: Maxime Ripard <firstname.lastname@example.org>
To: Icenowy Zheng <email@example.com>
Cc: Lorenzo Pieralisi <firstname.lastname@example.org>,
Andrew Murray <email@example.com>,
Bjorn Helgaas <firstname.lastname@example.org>, Chen-Yu Tsai <email@example.com>,
Rob Herring <firstname.lastname@example.org>,
Subject: Re: [RFC PATCH] PCI: dwc: add support for Allwinner SoCs' PCIe controller
Date: Wed, 6 May 2020 17:36:49 +0200 [thread overview]
Message-ID: <email@example.com> (raw)
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On Mon, Apr 20, 2020 at 04:18:58PM +0800, Icenowy Zheng wrote:
> 在 2020-04-06星期一的 10:27 +0200，Maxime Ripard写道：
> > Hi,
> > On Fri, Apr 03, 2020 at 12:05:49AM +0800, Icenowy Zheng wrote:
> > > The Allwinner H6 SoC uses DesignWare's PCIe controller to provide a
> > > PCIe
> > > host.
> > >
> > > However, on Allwinner H6, the PCIe host has bad MMIO, which needs
> > > to be
> > > workarounded. A workaround with the EL2 hypervisor functionality of
> > > ARM
> > > Cortex cores is now available, which wraps MMIO operations.
> > >
> > > This patch is going to add a driver for the DWC PCIe controller
> > > available in Allwinner SoCs, either the H6 one when wrapped by the
> > > hypervisor (so that the driver can consider it as an ordinary PCIe
> > > controller) or further not buggy ones.
> > >
> > > Signed-off-by: Icenowy Zheng <firstname.lastname@example.org>
> > > ---
> > > There's no device tree binding patch available, because I still
> > > have
> > > questions on the device tree compatible string. I want to use it to
> > > describe that this driver doesn't support the "native Allwinner H6
> > > PCIe
> > > controller", but a wrapped version with my hypervisor.
> > >
> > > I think supporting a "para-physical" device is some new thing, so
> > > this
> > > patch is RFC.
> > >
> > > My hypervisor is at , and some basic usage documentation is at
> > > .
> > >
> > >  https://github.com/Icenowy/aw-el2-barebone
> > > 
> > > https://forum.armbian.com/topic/13529-a-try-on-utilizing-h6-pcie-with-virtualization/
> > I'm a bit concerned to throw yet another mandatory, difficult to
> > update, component in the already quite long boot chain.
> > Getting fixes deployed in ATF or U-Boot is already pretty long,
> > having
> > another component in there will just make it worse, and it's another
> > hard to debug component that we throw into the mix.
> > And this prevents any use of virtualisation on the platform.
> > I haven't found an explanation on what that hypervisor is doing
> > exactly, but from a look at it it seems that it will trap all the
> > accesses to the PCIe memory region to emulate a regular space on top
> > of the restricted one we have?
> > If so, can't we do that from the kernel directly by using a memory
> > region that always fault with a fault handler like Framebuffer's
> > deferred_io is doing (drivers/video/fbdev/core/fb_defio.c) ?
> I don't know well about the memory management of the kernel. However,
> for PCIe memory space, the kernel allows simple ioremap() on it. So
> wrapping it shouldn't be so easy.
I'm not sure this would cause any trouble, it's worth exploring I guess. This
would solve all the current shortcomings.
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prev parent reply other threads:[~2020-05-06 15:36 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-02 16:05 [RFC PATCH] PCI: dwc: add support for Allwinner SoCs' PCIe controller Icenowy Zheng
2020-04-06 8:27 ` Maxime Ripard
2020-04-20 8:18 ` Icenowy Zheng
2020-05-06 15:36 ` Maxime Ripard [this message]
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