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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id 85sm1693266oie.17.2020.05.07.14.23.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 May 2020 14:23:47 -0700 (PDT) Received: (nullmailer pid 22453 invoked by uid 1000); Thu, 07 May 2020 21:23:47 -0000 Date: Thu, 7 May 2020 16:23:47 -0500 From: Rob Herring To: Pali =?iso-8859-1?Q?Roh=E1r?= Cc: Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Thomas Petazzoni , Lorenzo Pieralisi , Andrew Murray , Bjorn Helgaas , Remi Pommarel , Marek =?iso-8859-1?Q?Beh=FAn?= , Tomasz Maciej Nowak , Xogium , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: Re: [PATCH v4 07/12] PCI: aardvark: Add PHY support Message-ID: <20200507212347.GA22382@bogus> References: <20200430080625.26070-1-pali@kernel.org> <20200430080625.26070-8-pali@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20200430080625.26070-8-pali@kernel.org> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Thu, 30 Apr 2020 10:06:20 +0200, =?UTF-8?q?Pali=20Roh=C3=A1r?= wrote: > From: Marek Behún > > With recent proposed changes for U-Boot it is possible that bootloader > won't initialize the PHY for this controller (currently the PHY is > initialized regardless whether PCI is used in U-Boot, but with these > proposed changes the PHY is initialized only on request). > > Since the mvebu-a3700-comphy driver by Miquèl Raynal supports enabling > PCIe PHY, and since Linux' functionality should be independent on what > bootloader did, add code for enabling generic PHY if found in device OF > node. > > The mvebu-a3700-comphy driver does PHY powering via SMC calls to ARM > Trusted Firmware. The corresponding code in ARM Trusted Firmware skips > one register write which U-Boot does not: step 7 ("Enable TX"), see [1]. > Instead ARM Trusted Firmware expects PCIe driver to do this step, > probably because the register is in PCIe controller address space, > instead of PHY address space. We therefore add this step into the > advk_pcie_setup_hw function. > > [1] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/drivers/marvell/comphy/phy-comphy-3700.c?h=v2.3-rc2#n836 > > Signed-off-by: Marek Behún > Cc: Miquèl Raynal > --- > drivers/pci/controller/pci-aardvark.c | 69 +++++++++++++++++++++++++++ > 1 file changed, 69 insertions(+) > Reviewed-by: Rob Herring