Re: [PATCH v3] PCI/ASPM: Enable ASPM for bridge-to-bridge link

From: Bjorn Helgaas <helgaas@kernel.org>
To: Kai-Heng Feng <kai.heng.feng@canonical.com>
Cc: bhelgaas@google.com, Heiner Kallweit <hkallweit1@gmail.com>,
	"Rafael J. Wysocki" <rafael.j.wysocki@intel.com>,
	Keith Busch <keith.busch@intel.com>,
	Mika Westerberg <mika.westerberg@linux.intel.com>,
	Chris Packham <chris.packham@alliedtelesis.co.nz>,
	Yicong Yang <yangyicong@hisilicon.com>,
	Krzysztof Wilczynski <kw@linux.com>,
	"open list:PCI SUBSYSTEM" <linux-pci@vger.kernel.org>,
	open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v3] PCI/ASPM: Enable ASPM for bridge-to-bridge link
Date: Thu, 7 May 2020 17:19:53 -0500	[thread overview]
Message-ID: <20200507221953.GA36865@bjorn-Precision-5520> (raw)
In-Reply-To: <20200505173423.26968-1-kai.heng.feng@canonical.com>

On Wed, May 06, 2020 at 01:34:21AM +0800, Kai-Heng Feng wrote:
> The TI PCIe-to-PCI bridge prevents the Intel SoC from entering power
> state deeper than PC3 due to disabled ASPM, consumes lots of unnecessary
> power. On Windows ASPM L1 is enabled on the device and its upstream
> bridge, so it can make the Intel SoC reach PC8 or PC10 to save lots of
> power.
> 
> In short, ASPM always gets disabled on bridge-to-bridge link.
> 
> The special case was part of first ASPM introduction patch, commit
> 7d715a6c1ae5 ("PCI: add PCI Express ASPM support"). However, it didn't
> explain why ASPM needs to be disabled in special bridge-to-bridge case.
> 
> Let's remove the the special case, as PCIe spec already envisioned ASPM
> on bridge-to-bridge link.
> 
> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=207571
> Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com>

Applied to pci/aspm for v5.8, thanks!

I did keep your Reviewed-by, Mika.  If the fact that this applies only
to the PCIe-to-PCI/PCI-X case makes your reviewed-by invalid, just let
me know and I'll drop it.

> ---
> v3:
>  - Remove the special case completely.
> 
> v2: 
>  - Enable ASPM on root complex <-> bridge <-> bridge, instead of using
>    quirk.
>  drivers/pci/pcie/aspm.c | 10 ----------
>  1 file changed, 10 deletions(-)
> 
> diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
> index 2378ed692534..b17e5ffd31b1 100644
> --- a/drivers/pci/pcie/aspm.c
> +++ b/drivers/pci/pcie/aspm.c
> @@ -628,16 +628,6 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
>  
>  	/* Setup initial capable state. Will be updated later */
>  	link->aspm_capable = link->aspm_support;
> -	/*
> -	 * If the downstream component has pci bridge function, don't
> -	 * do ASPM for now.
> -	 */
> -	list_for_each_entry(child, &linkbus->devices, bus_list) {
> -		if (pci_pcie_type(child) == PCI_EXP_TYPE_PCI_BRIDGE) {
> -			link->aspm_disable = ASPM_STATE_ALL;
> -			break;
> -		}
> -	}
>  
>  	/* Get and check endpoint acceptable latencies */
>  	list_for_each_entry(child, &linkbus->devices, bus_list) {
> -- 
> 2.17.1
> 