From: Kishon Vijay Abraham I <kishon@ti.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
Rob Herring <robh+dt@kernel.org>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Robin Murphy <robin.murphy@arm.com>,
Tom Joseph <tjoseph@cadence.com>
Cc: <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <kishon@ti.com>
Subject: [PATCH v3 3/4] PCI: cadence: Fix to read 32-bit Vendor ID/Device ID property from DT
Date: Fri, 8 May 2020 18:36:45 +0530 [thread overview]
Message-ID: <20200508130646.23939-4-kishon@ti.com> (raw)
In-Reply-To: <20200508130646.23939-1-kishon@ti.com>
The PCI Bus Binding specification (IEEE Std 1275-1994 Revision 2.1 [1])
defines both Vendor ID and Device ID to be 32-bits. Fix
pcie-cadence-host.c driver to read 32-bit Vendor ID and Device ID
properties from device tree.
[1] -> https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Tom Joseph <tjoseph@cadence.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/pci/controller/cadence/pcie-cadence-host.c | 4 ++--
drivers/pci/controller/cadence/pcie-cadence.h | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
index 079692aa4da1..6ecebb79057a 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-host.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
@@ -243,10 +243,10 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
of_property_read_u32(np, "cdns,no-bar-match-nbits", &rc->no_bar_nbits);
rc->vendor_id = 0xffff;
- of_property_read_u16(np, "vendor-id", &rc->vendor_id);
+ of_property_read_u32(np, "vendor-id", &rc->vendor_id);
rc->device_id = 0xffff;
- of_property_read_u16(np, "device-id", &rc->device_id);
+ of_property_read_u32(np, "device-id", &rc->device_id);
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
pcie->reg_base = devm_ioremap_resource(dev, res);
diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
index cf1afd85c2f5..f349f5828a58 100644
--- a/drivers/pci/controller/cadence/pcie-cadence.h
+++ b/drivers/pci/controller/cadence/pcie-cadence.h
@@ -277,8 +277,8 @@ struct cdns_pcie_rc {
struct resource *bus_range;
void __iomem *cfg_base;
u32 no_bar_nbits;
- u16 vendor_id;
- u16 device_id;
+ u32 vendor_id;
+ u32 device_id;
};
/**
--
2.17.1
next prev parent reply other threads:[~2020-05-08 13:07 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-08 13:06 [PATCH v3 0/4] PCI: cadence: Deprecate inbound/outbound specific bindings Kishon Vijay Abraham I
2020-05-08 13:06 ` [PATCH v3 1/4] dt-bindings: " Kishon Vijay Abraham I
2020-05-08 13:06 ` [PATCH v3 2/4] PCI: cadence: Remove "cdns,max-outbound-regions" DT property Kishon Vijay Abraham I
2020-05-08 13:06 ` Kishon Vijay Abraham I [this message]
2020-05-08 13:06 ` [PATCH v3 4/4] PCI: cadence: Use "dma-ranges" instead of "cdns,no-bar-match-nbits" property Kishon Vijay Abraham I
2020-05-18 11:12 ` Kishon Vijay Abraham I
2020-05-19 17:11 ` Rob Herring
2020-05-21 3:30 ` Kishon Vijay Abraham I
2020-05-21 12:13 ` Kishon Vijay Abraham I
2020-05-18 14:57 ` [PATCH v3 0/4] PCI: cadence: Deprecate inbound/outbound specific bindings Lorenzo Pieralisi
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