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From: Sean V Kelley <sean.v.kelley@linux.intel.com>
To: bhelgaas@google.com
Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	"David E. Box" <david.e.box@linux.intel.com>
Subject: [PATCH V3 1/3] PCI: Add defines for Designated Vendor-Specific Capability
Date: Wed, 20 May 2020 11:06:38 -0700
Message-ID: <20200520180640.1911202-2-sean.v.kelley@linux.intel.com> (raw)
In-Reply-To: <20200520180640.1911202-1-sean.v.kelley@linux.intel.com>

From: "David E. Box" <david.e.box@linux.intel.com>

Add PCIe DVSEC extended capability ID and defines for the header offsets.
Defined in PCIe r5.0, sec 7.9.6.

Signed-off-by: David E. Box <david.e.box@linux.intel.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
---
 include/uapi/linux/pci_regs.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index f9701410d3b5..09daa9f07b6b 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -720,6 +720,7 @@
 #define PCI_EXT_CAP_ID_DPC	0x1D	/* Downstream Port Containment */
 #define PCI_EXT_CAP_ID_L1SS	0x1E	/* L1 PM Substates */
 #define PCI_EXT_CAP_ID_PTM	0x1F	/* Precision Time Measurement */
+#define PCI_EXT_CAP_ID_DVSEC	0x23	/* Designated Vendor-Specific */
 #define PCI_EXT_CAP_ID_DLF	0x25	/* Data Link Feature */
 #define PCI_EXT_CAP_ID_PL_16GT	0x26	/* Physical Layer 16.0 GT/s */
 #define PCI_EXT_CAP_ID_MAX	PCI_EXT_CAP_ID_PL_16GT
@@ -1062,6 +1063,10 @@
 #define  PCI_L1SS_CTL1_LTR_L12_TH_SCALE	0xe0000000  /* LTR_L1.2_THRESHOLD_Scale */
 #define PCI_L1SS_CTL2		0x0c	/* Control 2 Register */
 
+/* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */
+#define PCI_DVSEC_HEADER1		0x4 /* Vendor-Specific Header1 */
+#define PCI_DVSEC_HEADER2		0x8 /* Vendor-Specific Header2 */
+
 /* Data Link Feature */
 #define PCI_DLF_CAP		0x04	/* Capabilities Register */
 #define  PCI_DLF_EXCHANGE_ENABLE	0x80000000  /* Data Link Feature Exchange Enable */
-- 
2.26.2


  reply index

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-20 18:06 [PATCH V3 0/3] PCI: Add basic Compute eXpress Link DVSEC decode Sean V Kelley
2020-05-20 18:06 ` Sean V Kelley [this message]
2020-05-20 18:06 ` [PATCH V3 2/3] " Sean V Kelley
2020-05-20 18:06 ` [PATCH V3 3/3] PCI: Add helpers to enable/disable CXL.mem and CXL.cache Sean V Kelley
  -- strict thread matches above, loose matches on Subject: below --
2020-05-08  2:18 [PATCH v2 0/3] Intel Platform Monitoring Technology David E. Box
2020-07-14  6:23 ` [PATCH V3 1/3] PCI: Add defines for Designated Vendor-Specific Capability David E. Box
2020-07-14  8:40   ` Andy Shevchenko
2020-07-16  2:55   ` Randy Dunlap
2020-07-16 15:07     ` Bjorn Helgaas
2020-07-16 15:07       ` Randy Dunlap
2020-07-16 17:18     ` Alexander Duyck
2020-07-16 18:31       ` David E. Box

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