From: Rob Herring <robh@kernel.org>
To: Jon Derrick <jonathan.derrick@intel.com>
Cc: Bjorn Helgaas <helgaas@kernel.org>,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
linux-pci@vger.kernel.org,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Russell King <rmk+kernel@armlinux.org.uk>,
Christoph Hellwig <hch@lst.de>
Subject: Re: [PATCH v2 3/4] PCI: pci-bridge-emul: Update for PCIe 5.0 r1.0
Date: Wed, 20 May 2020 16:39:59 -0600 [thread overview]
Message-ID: <20200520223959.GA734903@bogus> (raw)
In-Reply-To: <20200511162117.6674-4-jonathan.derrick@intel.com>
On Mon, 11 May 2020 12:21:16 -0400, Jon Derrick wrote:
> Add missing bits from PCIe 4.0 and updates for PCIe 5.0 r1.0.
>
> PCIe 4.0:
> Device Status bit 6 - W1C - Emergency Power Reduction Detected
> Link Control bits 15:14 - RW - DRS Signaling Control
> Slot Control bit 13 - RW - Auto Slow Power Limit Disable
>
> PCIe 5.0:
> Slot Control bit 14 - RW - In-Band PD Disable
>
> Signed-off-by: Jon Derrick <jonathan.derrick@intel.com>
> ---
> drivers/pci/pci-bridge-emul.c | 31 ++++++++++++++++---------------
> 1 file changed, 16 insertions(+), 15 deletions(-)
>
Acked-by: Rob Herring <robh@kernel.org>
next prev parent reply other threads:[~2020-05-20 22:40 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-11 16:21 [PATCH v2 0/4] Align PCI Emul Bridge to PCIe 5.0 Jon Derrick
2020-05-11 16:21 ` [PATCH v2 1/4] PCI: pci-bridge-emul: Fix PCIe bit conflicts Jon Derrick
2020-05-11 16:21 ` [PATCH v2 2/4] PCI: pci-bridge-emul: Fix Root Cap/Status comment Jon Derrick
2020-05-11 16:21 ` [PATCH v2 3/4] PCI: pci-bridge-emul: Update for PCIe 5.0 r1.0 Jon Derrick
2020-05-20 22:39 ` Rob Herring [this message]
2020-05-11 16:21 ` [PATCH v2 4/4] PCI: pci-bridge-emul: Eliminate the 'reserved' member Jon Derrick
2020-05-20 22:41 ` Rob Herring
2020-05-22 11:42 ` [PATCH v2 0/4] Align PCI Emul Bridge to PCIe 5.0 Lorenzo Pieralisi
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