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Wed, 29 Jul 2020 11:56:56 -0700 (PDT) Received: from xps15 ([64.188.179.252]) by smtp.gmail.com with ESMTPSA id u6sm1576835ilk.13.2020.07.29.11.56.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jul 2020 11:56:55 -0700 (PDT) Received: (nullmailer pid 593935 invoked by uid 1000); Wed, 29 Jul 2020 18:56:54 -0000 Date: Wed, 29 Jul 2020 12:56:54 -0600 From: Rob Herring To: Vidya Sagar Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com, lorenzo.pieralisi@arm.com, bhelgaas@google.com, amurray@thegoodpenguin.co.uk, thierry.reding@gmail.com, jonathanh@nvidia.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kthota@nvidia.com, mmaddireddy@nvidia.com, sagar.tv@gmail.com Subject: Re: [PATCH 1/2] PCI: dwc: Add support to handle prefetchable memory separately Message-ID: <20200729185654.GA585891@bogus> References: <20200602100940.10575-1-vidyas@nvidia.com> <20200602100940.10575-2-vidyas@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200602100940.10575-2-vidyas@nvidia.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Tue, Jun 02, 2020 at 03:39:39PM +0530, Vidya Sagar wrote: > Add required structure members to struct pcie_port to handle prefetchable > memory aperture separately from non-prefetchable memory aperture so that > any dependency on the order of their appearance in the 'ranges' property > of the respective PCIe device tree node can be removed. > > Signed-off-by: Vidya Sagar > --- > .../pci/controller/dwc/pcie-designware-host.c | 26 ++++++++++++------- > drivers/pci/controller/dwc/pcie-designware.h | 4 +++ > 2 files changed, 21 insertions(+), 9 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > index 42fbfe2a1b8f..6f06d6bd9f00 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > @@ -363,13 +363,23 @@ int dw_pcie_host_init(struct pcie_port *pp) > pp->io_base = pci_pio_to_address(pp->io->start); > break; > case IORESOURCE_MEM: > - pp->mem = win->res; > - pp->mem->name = "MEM"; > - mem_size = resource_size(pp->mem); > - if (upper_32_bits(mem_size)) > - dev_warn(dev, "MEM resource size exceeds max for 32 bits\n"); > - pp->mem_size = mem_size; > - pp->mem_bus_addr = pp->mem->start - win->offset; > + if (win->res->flags & IORESOURCE_PREFETCH) { > + pp->prefetch = win->res; > + pp->prefetch->name = "PREFETCH"; > + pp->prefetch_base = pp->prefetch->start; > + pp->prefetch_size = resource_size(pp->prefetch); > + pp->perfetch_bus_addr = pp->prefetch->start - > + win->offset; > + } else { > + pp->mem = win->res; > + pp->mem->name = "MEM"; > + pp->mem_base = pp->mem->start; > + mem_size = resource_size(pp->mem); > + if (upper_32_bits(mem_size)) > + dev_warn(dev, "MEM resource size exceeds max for 32 bits\n"); > + pp->mem_size = mem_size; > + pp->mem_bus_addr = pp->mem->start - win->offset; > + } > break; > case 0: > pp->cfg = win->res; > @@ -394,8 +404,6 @@ int dw_pcie_host_init(struct pcie_port *pp) > } > } > > - pp->mem_base = pp->mem->start; > - > if (!pp->va_cfg0_base) { > pp->va_cfg0_base = devm_pci_remap_cfgspace(dev, > pp->cfg0_base, pp->cfg0_size); > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > index 656e00f8fbeb..c87c1b2a1177 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.h > +++ b/drivers/pci/controller/dwc/pcie-designware.h > @@ -186,9 +186,13 @@ struct pcie_port { > u64 mem_base; > phys_addr_t mem_bus_addr; > u32 mem_size; > + u64 prefetch_base; > + phys_addr_t perfetch_bus_addr; > + u64 prefetch_size; There's no reason to store these for all eternity as they are used in one place and already stored as resources in bridge->windows. I have a patch series removing most of this that I will post in a few days. There's a WIP branch, pci-dw-config-access, in my kernel.org tree. Mostly you just need the bridge ptr which is isn't currently saved in pcie_port. Rob