From: "Saheed O. Bolarinwa" <refactormyself@gmail.com>
To: helgaas@kernel.org
Cc: "Saheed O. Bolarinwa" <refactormyself@gmail.com>,
bjorn@helgaas.com, skhan@linuxfoundation.org,
linux-pci@vger.kernel.org,
linux-kernel-mentees@lists.linuxfoundation.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v4 11/12] PCI/ASPM: Check if pcie_capability_read_*() reads ~0
Date: Fri, 31 Jul 2020 13:43:28 +0200 [thread overview]
Message-ID: <20200731114329.100848-4-refactormyself@gmail.com> (raw)
In-Reply-To: <20200731114329.100848-1-refactormyself@gmail.com>
On failure pcie_capability_read_*() sets it's last parameter, val
to 0. However, with Patch 12/12, it is possible that val is set
to ~0 on failure. This would introduce a bug because
(x & x) == (~0 & x).
Since ~0 is an invalid value in here,
Add extra check for ~0 to the if condition to confirm failure.
Suggested-by: Bjorn Helgaas <bjorn@helgaas.com>
Signed-off-by: Saheed O. Bolarinwa <refactormyself@gmail.com>
---
drivers/pci/pcie/aspm.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index b17e5ffd31b1..5e84a5ee94b0 100644
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -223,7 +223,7 @@ static bool pcie_retrain_link(struct pcie_link_state *link)
end_jiffies = jiffies + LINK_RETRAIN_TIMEOUT;
do {
pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
- if (!(reg16 & PCI_EXP_LNKSTA_LT))
+ if ((reg16 == (u16)~0) || !(reg16 & PCI_EXP_LNKSTA_LT))
break;
msleep(1);
} while (time_before(jiffies, end_jiffies));
@@ -250,23 +250,23 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
/* Check downstream component if bit Slot Clock Configuration is 1 */
pcie_capability_read_word(child, PCI_EXP_LNKSTA, ®16);
- if (!(reg16 & PCI_EXP_LNKSTA_SLC))
+ if ((reg16 == (u16)~0) || !(reg16 & PCI_EXP_LNKSTA_SLC))
same_clock = 0;
/* Check upstream component if bit Slot Clock Configuration is 1 */
pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
- if (!(reg16 & PCI_EXP_LNKSTA_SLC))
+ if ((reg16 == (u16)~0) || !(reg16 & PCI_EXP_LNKSTA_SLC))
same_clock = 0;
/* Port might be already in common clock mode */
pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
- if (same_clock && (reg16 & PCI_EXP_LNKCTL_CCC)) {
+ if ((reg16 != (u16)~0) && same_clock && (reg16 & PCI_EXP_LNKCTL_CCC)) {
bool consistent = true;
list_for_each_entry(child, &linkbus->devices, bus_list) {
pcie_capability_read_word(child, PCI_EXP_LNKCTL,
®16);
- if (!(reg16 & PCI_EXP_LNKCTL_CCC)) {
+ if ((reg16 == (u16)~0) || !(reg16 & PCI_EXP_LNKCTL_CCC)) {
consistent = false;
break;
}
--
2.18.4
next prev parent reply other threads:[~2020-07-31 12:43 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-31 11:43 [PATCH v4 08/12] PCI: Check if pcie_capability_read_*() reads ~0 Saheed O. Bolarinwa
2020-07-31 11:43 ` [PATCH v4 09/12] PCI/PM: " Saheed O. Bolarinwa
2020-07-31 11:43 ` [PATCH v4 10/12] PCI/AER: " Saheed O. Bolarinwa
2020-07-31 11:43 ` Saheed O. Bolarinwa [this message]
2020-07-31 11:43 ` [PATCH v4 12/12] PCI: Remove '*val = 0' from pcie_capability_read_*() Saheed O. Bolarinwa
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