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Date:   Fri, 4 Sep 2020 08:45:01 -0300
From:   Jason Gunthorpe <jgg@nvidia.com>
To:     Thierry Reding <thierry.reding@gmail.com>
CC:     Bjorn Helgaas <bhelgaas@google.com>,
        Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
        Jonathan Hunter <jonathanh@nvidia.com>,
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Subject: Re: [PATCH] PCI: tegra: Convert to MSI domains
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References: <20200904105613.444945-1-thierry.reding@gmail.com>
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On Fri, Sep 04, 2020 at 12:56:13PM +0200, Thierry Reding wrote:
> +static void tegra_msi_irq_mask(struct irq_data *d)
> +{
> +	struct tegra_msi *msi = irq_data_get_irq_chip_data(d);
> +	struct tegra_pcie *pcie = msi_to_pcie(msi);
> +	unsigned int index = d->hwirq / 32;
> +	u32 value;
> +
> +	value = afi_readl(pcie, AFI_MSI_EN_VEC(index));
> +	value &= ~BIT(d->hwirq % 32);
> +	afi_writel(pcie, value, AFI_MSI_EN_VEC(index));
> +}

Do these need a flushing write? The Mask operation should be synchronous?

Thanks,
Jason