On Fri, Sep 04, 2020 at 08:45:01AM -0300, Jason Gunthorpe wrote:
> On Fri, Sep 04, 2020 at 12:56:13PM +0200, Thierry Reding wrote:
> > +static void tegra_msi_irq_mask(struct irq_data *d)
> > +{
> > +	struct tegra_msi *msi = irq_data_get_irq_chip_data(d);
> > +	struct tegra_pcie *pcie = msi_to_pcie(msi);
> > +	unsigned int index = d->hwirq / 32;
> > +	u32 value;
> > +
> > +	value = afi_readl(pcie, AFI_MSI_EN_VEC(index));
> > +	value &= ~BIT(d->hwirq % 32);
> > +	afi_writel(pcie, value, AFI_MSI_EN_VEC(index));
> > +}
> 
> Do these need a flushing write? The Mask operation should be synchronous?

Did you mean a flushing read? We typically flush out writes by reading
from the same register. Another write wouldn't guarantee that both
writes are actually flushed to hardware, would it?

Yes, that sounds like a good idea. It seems to work fine without, but
that may just be a coincidence.

Thierry