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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id s124sm382882oig.6.2020.09.30.08.23.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Sep 2020 08:23:22 -0700 (PDT) Received: (nullmailer pid 2896316 invoked by uid 1000); Wed, 30 Sep 2020 15:23:17 -0000 Date: Wed, 30 Sep 2020 10:23:17 -0500 From: Rob Herring To: Chuanjia Liu Cc: Bjorn Helgaas , Lorenzo Pieralisi , Matthias Brugger , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, yong.wu@mediatek.com, Frank Wunderlich , Ryder Lee Subject: Re: [PATCH v6 2/4] PCI: mediatek: Add new method to get shared pcie-cfg base and irq Message-ID: <20200930152317.GA2891120@bogus> References: <20200914112659.7091-1-chuanjia.liu@mediatek.com> <20200914112659.7091-3-chuanjia.liu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200914112659.7091-3-chuanjia.liu@mediatek.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Mon, Sep 14, 2020 at 07:26:57PM +0800, Chuanjia Liu wrote: > Add new method to get shared pcie-cfg base and pcie irq for > new dts format. > > Signed-off-by: Chuanjia Liu > Acked-by: Ryder Lee > --- > drivers/pci/controller/pcie-mediatek.c | 23 ++++++++++++++++++++++- > 1 file changed, 22 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c > index cf4c18f0c25a..5b915eb0cf1e 100644 > --- a/drivers/pci/controller/pcie-mediatek.c > +++ b/drivers/pci/controller/pcie-mediatek.c > @@ -14,6 +14,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -23,6 +24,7 @@ > #include > #include > #include > +#include > #include > > #include "../pci.h" > @@ -205,6 +207,7 @@ struct mtk_pcie_port { > * struct mtk_pcie - PCIe host information > * @dev: pointer to PCIe device > * @base: IO mapped register base > + * @cfg: IO mapped register map for PCIe config > * @free_ck: free-run reference clock > * @mem: non-prefetchable memory resource > * @ports: pointer to PCIe port information > @@ -213,6 +216,7 @@ struct mtk_pcie_port { > struct mtk_pcie { > struct device *dev; > void __iomem *base; > + struct regmap *cfg; > struct clk *free_ck; > > struct list_head ports; > @@ -648,7 +652,11 @@ static int mtk_pcie_setup_irq(struct mtk_pcie_port *port, > return err; > } > > - port->irq = platform_get_irq(pdev, port->slot); > + if (of_find_property(dev->of_node, "interrupt-names", NULL)) > + port->irq = platform_get_irq_byname(pdev, "pcie_irq"); Not really any point in having a name with a single interrupt. > + else > + port->irq = platform_get_irq(pdev, port->slot); With the new binding, slot is always 0, right? Then you don't need any change here. > + > if (port->irq < 0) > return port->irq; > > @@ -680,6 +688,10 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) > val |= PCIE_CSR_LTSSM_EN(port->slot) | > PCIE_CSR_ASPM_L1_EN(port->slot); > writel(val, pcie->base + PCIE_SYS_CFG_V2); > + } else if (pcie->cfg) { > + val = PCIE_CSR_LTSSM_EN(port->slot) | > + PCIE_CSR_ASPM_L1_EN(port->slot); > + regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val, val); > } > > /* Assert all reset signals */ > @@ -983,6 +995,7 @@ static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie) > struct device *dev = pcie->dev; > struct platform_device *pdev = to_platform_device(dev); > struct resource *regs; > + struct device_node *cfg_node; > int err; > > /* get shared registers, which are optional */ > @@ -995,6 +1008,14 @@ static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie) > } > } > > + cfg_node = of_find_compatible_node(NULL, NULL, > + "mediatek,generic-pciecfg"); > + if (cfg_node) { > + pcie->cfg = syscon_node_to_regmap(cfg_node); > + if (IS_ERR(pcie->cfg)) > + return PTR_ERR(pcie->cfg); > + } > + > pcie->free_ck = devm_clk_get(dev, "free_ck"); > if (IS_ERR(pcie->free_ck)) { > if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER) > -- > 2.18.0