Re: [PATCH v2 5/5] PCI: qcom: Add support for configuring BDF to SID mapping for SM8250

[Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>]

Hi Stan,

On Thu, Oct 01, 2020 at 12:46:46AM +0300, Stanimir Varbanov wrote:
> Hi Mani,
> 
> On 9/30/20 6:09 PM, Manivannan Sadhasivam wrote:
> > For SM8250, we need to write the BDF to SID mapping in PCIe controller
> > register space for proper working. This is accomplished by extracting
> > the BDF and SID values from "iommu-map" property in DT and writing those
> > in the register address calculated from the hash value of BDF. In case
> > of collisions, the index of the next entry will also be written.
> 
> This describes what the patch is doing. But why? Is that done in the
> other DWC low-level drivers or this is qcom specialty?
> 

AFAIK, only some NXP SoCs deal with similar kind of mapping but right now
this is a Qcom only stuff.

> > 
> > For the sake of it, let's introduce a "config_sid" callback and do it
> > conditionally for SM8250.
> > 
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > ---
> >  drivers/pci/controller/dwc/Kconfig     |   1 +
> >  drivers/pci/controller/dwc/pcie-qcom.c | 138 +++++++++++++++++++++++++
> >  2 files changed, 139 insertions(+)
> > 

[...]

> > +
> > +/* sid info structure */
> > +struct qcom_pcie_sid_info_t {
> 
> why _t postfix? Maybe qcom_pcie_sid ?
> 

Just to differentiate the struct name and its variable. But I can
remove the _t suffix.

> SID - Stream ID ?
> 

Yes! Will expand in commit message also.

> > +	u16 bdf;
> > +	u8 pcie_sid;
> > +	u8 hash;
> > +	u32 smmu_sid;
> > +	u32 value;
> >  };
> >  
> >  struct qcom_pcie {
> > @@ -193,6 +208,8 @@ struct qcom_pcie {
> >  	struct phy *phy;
> >  	struct gpio_desc *reset;
> >  	const struct qcom_pcie_ops *ops;
> > +	struct qcom_pcie_sid_info_t *sid_info;
> > +	u32 sid_info_len;
> >  	int gen;
> >  };
> >  
> > @@ -1257,6 +1274,120 @@ static int qcom_pcie_link_up(struct dw_pcie *pci)
> >  	return !!(val & PCI_EXP_LNKSTA_DLLLA);
> >  }
> >  
> > +static int qcom_pcie_get_iommu_map(struct qcom_pcie *pcie)
> > +{
> > +	/* iommu map structure */
> > +	struct {
> > +		u32 bdf;
> > +		u32 phandle;
> > +		u32 smmu_sid;
> > +		u32 smmu_sid_len;
> > +	} *map;
> > +	struct device *dev = pcie->pci->dev;
> > +	int i, size = 0;
> > +	u32 smmu_sid_base;
> > +
> > +	of_get_property(dev->of_node, "iommu-map", &size);
> > +	if (!size)
> > +		return 0;
> > +
> > +	map = kzalloc(size, GFP_KERNEL);
> > +	if (!map)
> > +		return -ENOMEM;
> > +
> > +	of_property_read_u32_array(dev->of_node,
> > +		"iommu-map", (u32 *)map, size / sizeof(u32));
> 
> iommu-map is a standard DT property why we have to parse it manually?
> 

So right now we don't have a way to pass this information from DT. And there
is no IOMMU API to parse the fields also. We need to extract this information
to program the hash tables (BDF, SID) as the mapping between BDF and SID is not
1:1 in SM8250.

Perhaps I can add this information in commit message.

> > +
> > +	pcie->sid_info_len = size / (sizeof(*map));
> > +	pcie->sid_info = devm_kcalloc(dev, pcie->sid_info_len,
> > +				sizeof(*pcie->sid_info), GFP_KERNEL);
> > +	if (!pcie->sid_info) {
> > +		kfree(map);
> > +		return -ENOMEM;
> > +	}
> > +
> > +	/* Extract the SMMU SID base from the first entry of iommu-map */
> > +	smmu_sid_base = map[0].smmu_sid;
> > +	for (i = 0; i < pcie->sid_info_len; i++) {
> > +		pcie->sid_info[i].bdf = map[i].bdf;
> > +		pcie->sid_info[i].smmu_sid = map[i].smmu_sid;
> > +		pcie->sid_info[i].pcie_sid =
> > +				pcie->sid_info[i].smmu_sid - smmu_sid_base;
> > +	}
> > +
> > +	kfree(map);
> > +
> > +	return 0;
> > +}
> > +
> > +static int qcom_pcie_config_sid_sm8250(struct qcom_pcie *pcie)
> > +{
> > +	void __iomem *bdf_to_sid_base = pcie->parf +
> > +		PCIE20_PARF_BDF_TO_SID_TABLE_N;
> > +	u8 qcom_pcie_crc8_table[CRC8_TABLE_SIZE];
> > +	int ret, i;
> > +
> > +	ret = qcom_pcie_get_iommu_map(pcie);
> > +	if (ret)
> > +		return ret;
> > +
> > +	if (!pcie->sid_info)
> > +		return 0;
> > +
> > +	crc8_populate_msb(qcom_pcie_crc8_table, QCOM_PCIE_CRC8_POLYNOMIAL);
> > +
> > +	/* Registers need to be zero out first */
> > +	memset_io(bdf_to_sid_base, 0, CRC8_TABLE_SIZE * sizeof(u32));
> > +
> > +	/* Initial setup for boot */
> 
> Could you elaborate more what the code below is trying to achieve. Is
> that connected to bootloaders?
> 

No. This is trying to program the hash tables for initial boot but I think this
doesn't make sense here as it will be done all the time. I'll just remove this
comment.

Thanks,
Mani