From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9115CC4363A for ; Thu, 8 Oct 2020 15:08:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3854021924 for ; Thu, 8 Oct 2020 15:08:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730786AbgJHPI0 (ORCPT ); Thu, 8 Oct 2020 11:08:26 -0400 Received: from foss.arm.com ([217.140.110.172]:33994 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729833AbgJHPI0 (ORCPT ); Thu, 8 Oct 2020 11:08:26 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B95EB1063; Thu, 8 Oct 2020 08:08:25 -0700 (PDT) Received: from e121166-lin.cambridge.arm.com (e121166-lin.cambridge.arm.com [10.1.196.255]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 83FE23F70D; Thu, 8 Oct 2020 08:08:24 -0700 (PDT) Date: Thu, 8 Oct 2020 16:08:19 +0100 From: Lorenzo Pieralisi To: Kishon Vijay Abraham I Cc: Rob Herring , Gustavo Pimentel , "Z.q. Hou" , "linux-kernel@vger.kernel.org" , PCI , Bjorn Helgaas , Michael Walle , Ard Biesheuvel Subject: Re: [PATCH] PCI: dwc: Added link up check in map_bus of dw_child_pcie_ops Message-ID: <20201008150819.GA3871@e121166-lin.cambridge.arm.com> References: <20200928093911.GB12010@e121166-lin.cambridge.arm.com> <9ac53f04-f2e8-c5f9-e1f7-e54270ec55a0@ti.com> <67ac959f-561e-d1a0-2d89-9a85d5f92c72@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <67ac959f-561e-d1a0-2d89-9a85d5f92c72@ti.com> User-Agent: Mutt/1.9.4 (2018-02-28) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Thu, Oct 01, 2020 at 07:02:04PM +0530, Kishon Vijay Abraham I wrote: [...] > >> Yeah, I don't see any registers in the DRA7x PCIe wrapper for disabling > >> error forwarding. > > > > It's a DWC port logic register AFAICT, but perhaps not present in all versions. > > Okay. I see there's a register PCIECTRL_PL_AXIS_SLV_ERR_RESP which has a > reset value of 0. > > It has four bit-fields, RESET_TIMEOUT_ERR_MAP, NO_VID_ERR_MAP, > DBI_ERR_MAP and SLAVE_ERR_MAP. I'm not seeing any difference in behavior > if I set all these bits. Maybe it requires platform support too. I'll > check this with our design team. > > Meanwhile would it be okay to add linkup check atleast for DRA7X so that > we could have it booting in linux-next? Do you mind sending a patch on top of my pci/dwc please ? Thanks, Lorenzo