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Date:   Fri, 9 Oct 2020 10:12:18 -0300
From:   Jason Gunthorpe <jgg@nvidia.com>
To:     "Raj, Ashok" <ashok.raj@intel.com>
CC:     Thomas Gleixner <tglx@linutronix.de>,
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Subject: Re: [PATCH v3 11/18] dmaengine: idxd: ims setup for the vdcm
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On Fri, Oct 09, 2020 at 06:02:09AM -0700, Raj, Ashok wrote:
> On Fri, Oct 09, 2020 at 09:49:45AM -0300, Jason Gunthorpe wrote:
> > On Fri, Oct 09, 2020 at 05:43:07AM -0700, Raj, Ashok wrote:
> > > On Fri, Oct 09, 2020 at 08:57:37AM -0300, Jason Gunthorpe wrote:
> > > > On Thu, Oct 08, 2020 at 06:22:31PM -0700, Raj, Ashok wrote:
> > > > 
> > > > > Not randomly put there Jason :-).. There is a good reason for it. 
> > > > 
> > > > Sure the PASID value being associated with the IRQ make sense, but
> > > > combining that register with the interrupt mask is just a compltely
> > > > random thing to do.
> > > 
> > > Hummm... Not sure what you are complaining.. but in any case giving
> > > hardware a more efficient way to store interrupt entries breaking any
> > > boundaries that maybe implied by the spec is why IMS was defined.
> > 
> > I'm saying this PASID stuff is just some HW detail of IDXD and nothing
> > that the core irqchip code should concern itself with
> 
> Ok, so you are saying this is device specific why is generic framework
> having to worry about the PASID stuff? 
> 
> I thought we are consolidating code that otherwise similar drivers would
> require anyway. I thought that's what Thomas was accomplishing with the new
> framework.

My point is why would another driver combine PASID and the IRQ mask in
one register? There is no spec saying to do this, no common design
reason, it has *nothing* to do with the IRQ mask other than IDXD made
a completely random choice to put the IRQ mask and PASID in the same 32
bit register.

At the very least we should see a bunch more drivers doing this same
thing before we declare some kind of pattern

Jason