From: "Raj, Ashok" <ashok.raj@intel.com>
To: Jason Gunthorpe <jgg@nvidia.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Dave Jiang <dave.jiang@intel.com>,
vkoul@kernel.org, megha.dey@intel.com, maz@kernel.org,
bhelgaas@google.com, alex.williamson@redhat.com,
jacob.jun.pan@intel.com, yi.l.liu@intel.com, baolu.lu@intel.com,
kevin.tian@intel.com, sanjay.k.kumar@intel.com,
tony.luck@intel.com, jing.lin@intel.com,
dan.j.williams@intel.com, kwankhede@nvidia.com,
eric.auger@redhat.com, parav@mellanox.com, rafael@kernel.org,
netanelg@mellanox.com, shahafs@mellanox.com,
yan.y.zhao@linux.intel.com, pbonzini@redhat.com,
samuel.ortiz@intel.com, mona.hossain@intel.com,
dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org,
x86@kernel.org, linux-pci@vger.kernel.org, kvm@vger.kernel.org,
Ashok Raj <ashok.raj@intel.com>
Subject: Re: [PATCH v3 11/18] dmaengine: idxd: ims setup for the vdcm
Date: Fri, 9 Oct 2020 06:40:05 -0700 [thread overview]
Message-ID: <20201009134005.GD63643@otc-nc-03> (raw)
In-Reply-To: <20201009131218.GK4734@nvidia.com>
On Fri, Oct 09, 2020 at 10:12:18AM -0300, Jason Gunthorpe wrote:
> On Fri, Oct 09, 2020 at 06:02:09AM -0700, Raj, Ashok wrote:
> > On Fri, Oct 09, 2020 at 09:49:45AM -0300, Jason Gunthorpe wrote:
> > > On Fri, Oct 09, 2020 at 05:43:07AM -0700, Raj, Ashok wrote:
> > > > On Fri, Oct 09, 2020 at 08:57:37AM -0300, Jason Gunthorpe wrote:
> > > > > On Thu, Oct 08, 2020 at 06:22:31PM -0700, Raj, Ashok wrote:
> > > > >
> > > > > > Not randomly put there Jason :-).. There is a good reason for it.
> > > > >
> > > > > Sure the PASID value being associated with the IRQ make sense, but
> > > > > combining that register with the interrupt mask is just a compltely
> > > > > random thing to do.
> > > >
> > > > Hummm... Not sure what you are complaining.. but in any case giving
> > > > hardware a more efficient way to store interrupt entries breaking any
> > > > boundaries that maybe implied by the spec is why IMS was defined.
> > >
> > > I'm saying this PASID stuff is just some HW detail of IDXD and nothing
> > > that the core irqchip code should concern itself with
> >
> > Ok, so you are saying this is device specific why is generic framework
> > having to worry about the PASID stuff?
> >
> > I thought we are consolidating code that otherwise similar drivers would
> > require anyway. I thought that's what Thomas was accomplishing with the new
> > framework.
>
> My point is why would another driver combine PASID and the IRQ mask in
> one register? There is no spec saying to do this, no common design
IMS is a concept. How a device organizes its interrupt data is completely
hardware specific. Some vendor could keep them organized like how MSIx is
done today, and put PASID's in a separate offset. Or put all interrupt
related entries all in one place like how idxd handles it today.
Cheers,
Ashok
next prev parent reply other threads:[~2020-10-09 13:40 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <160021207013.67751.8220471499908137671.stgit@djiang5-desk3.ch.intel.com>
2020-09-15 23:27 ` [PATCH v3 01/18] irqchip: Add IMS (Interrupt Message Storage) driver Dave Jiang
2020-09-30 18:23 ` Thomas Gleixner
2020-10-01 22:59 ` Dey, Megha
2020-09-15 23:27 ` [PATCH v3 02/18] iommu/vt-d: Add DEV-MSI support Dave Jiang
2020-09-30 18:32 ` Thomas Gleixner
2020-10-01 23:26 ` Dey, Megha
2020-10-02 11:13 ` Thomas Gleixner
2020-10-08 7:54 ` David Woodhouse
2020-10-20 21:42 ` Dey, Megha
2020-09-15 23:28 ` [PATCH v3 05/18] dmaengine: idxd: add IMS support in base driver Dave Jiang
2020-09-30 18:47 ` Thomas Gleixner
2020-09-30 18:51 ` Jason Gunthorpe
2020-09-30 21:48 ` Thomas Gleixner
2020-09-30 21:49 ` Raj, Ashok
2020-09-30 21:57 ` Thomas Gleixner
2020-10-01 1:07 ` Raj, Ashok
2020-10-01 8:44 ` Thomas Gleixner
2020-09-30 22:38 ` Jason Gunthorpe
2020-10-01 20:48 ` Dave Jiang
2020-09-15 23:28 ` [PATCH v3 07/18] dmaengine: idxd: add basic mdev registration and helper functions Dave Jiang
2020-09-15 23:28 ` [PATCH v3 10/18] dmaengine: idxd: virtual device commands emulation Dave Jiang
2020-09-15 23:28 ` [PATCH v3 12/18] dmaengine: idxd: add mdev type as a new wq type Dave Jiang
2020-09-15 23:29 ` [PATCH v3 13/18] dmaengine: idxd: add dedicated wq mdev type Dave Jiang
2020-09-15 23:29 ` [PATCH v3 14/18] dmaengine: idxd: add new wq state for mdev Dave Jiang
2020-09-15 23:29 ` [PATCH v3 15/18] dmaengine: idxd: add error notification from host driver to mediated device Dave Jiang
2020-09-15 23:29 ` [PATCH v3 16/18] dmaengine: idxd: add ABI documentation for mediated device support Dave Jiang
2020-09-17 15:06 ` [PATCH v3 00/18] Add VFIO mediated device support and DEV-MSI support for the idxd driver Jason Gunthorpe
2020-09-17 17:15 ` Dave Jiang
2020-09-17 17:27 ` Jason Gunthorpe
2020-09-17 17:30 ` Alex Williamson
2020-09-17 17:37 ` Jason Gunthorpe
[not found] ` <160021248280.67751.12525558281536923518.stgit@djiang5-desk3.ch.intel.com>
2020-09-30 18:36 ` [PATCH v3 04/18] dmaengine: idxd: add interrupt handle request support Thomas Gleixner
2020-10-01 20:16 ` Dave Jiang
[not found] ` <160021253189.67751.12686144284999931703.stgit@djiang5-desk3.ch.intel.com>
2020-09-30 19:57 ` [PATCH v3 11/18] dmaengine: idxd: ims setup for the vdcm Thomas Gleixner
2020-10-07 21:54 ` Dave Jiang
2020-10-08 7:39 ` Thomas Gleixner
2020-10-08 16:51 ` Dave Jiang
2020-10-08 23:17 ` Thomas Gleixner
2020-10-08 23:32 ` Jason Gunthorpe
2020-10-09 0:27 ` Dave Jiang
2020-10-09 1:22 ` Raj, Ashok
2020-10-09 11:57 ` Jason Gunthorpe
2020-10-09 12:43 ` Raj, Ashok
2020-10-09 12:49 ` Jason Gunthorpe
2020-10-09 13:02 ` Raj, Ashok
2020-10-09 13:12 ` Jason Gunthorpe
2020-10-09 13:40 ` Raj, Ashok [this message]
2020-10-09 14:44 ` Thomas Gleixner
2020-10-09 14:52 ` Jason Gunthorpe
2020-10-09 16:02 ` Thomas Gleixner
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