From: Vidya Sagar <vidyas@nvidia.com>
To: <lorenzo.pieralisi@arm.com>, <robh+dt@kernel.org>,
<bhelgaas@google.com>, <thierry.reding@gmail.com>,
<jonathanh@nvidia.com>, <amanharitsh123@gmail.com>,
<dinghao.liu@zju.edu.cn>, <kw@linux.com>
Cc: <linux-pci@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <kthota@nvidia.com>,
<mmaddireddy@nvidia.com>, <vidyas@nvidia.com>,
<sagar.tv@gmail.com>
Subject: [PATCH 3/4] PCI: tegra: Set DesignWare IP version
Date: Mon, 26 Oct 2020 12:24:58 +0530
Message-ID: <20201026065459.28509-4-vidyas@nvidia.com> (raw)
In-Reply-To: <20201026065459.28509-1-vidyas@nvidia.com>
Set the DesignWare IP version for Tegra194 to 0x490A. This would be used
by the DesigWare sub-system to do any version specific configuration
(Ex:- TD bit programming for ECRC).
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
drivers/pci/controller/dwc/pcie-tegra194.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 7a0c64436861..253d91033bc3 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -2011,6 +2011,7 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
pci->ops = &tegra_dw_pcie_ops;
pci->n_fts[0] = N_FTS_VAL;
pci->n_fts[1] = FTS_VAL;
+ pci->version = 0x490A;
pp = &pci->pp;
pcie->dev = &pdev->dev;
--
2.17.1
next prev parent reply index
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-26 6:54 [PATCH 0/4] Enhancements to Tegra194 PCIe driver Vidya Sagar
2020-10-26 6:54 ` [PATCH 1/4] PCI: tegra: Fix ASPM-L1SS advertisement disable code Vidya Sagar
2020-10-26 6:54 ` [PATCH 2/4] PCI: tegra: Map configuration space as strongly ordered Vidya Sagar
2020-10-26 18:41 ` Rob Herring
2020-10-26 6:54 ` Vidya Sagar [this message]
2020-10-26 6:54 ` [PATCH 4/4] PCI: tegra: Handle error conditions properly Vidya Sagar
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