From: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, lorenzo.pieralisi@arm.com,
robh+dt@kernel.org, bhelgaas@google.com, shawnguo@kernel.org,
leoyang.li@nxp.com, gustavo.pimentel@synopsys.com
Cc: minghuan.Lian@nxp.com, mingkai.hu@nxp.com, roy.zang@nxp.com,
Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Subject: [PATCHv2 5/7] dt-bindings: pci: layerscape-pci: Update the description of SCFG property
Date: Tue, 27 Oct 2020 15:29:59 +0800 [thread overview]
Message-ID: <20201027073001.41808-6-Zhiqiang.Hou@nxp.com> (raw)
In-Reply-To: <20201027073001.41808-1-Zhiqiang.Hou@nxp.com>
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Update the description of the second entry of 'fsl,pcie-scfg' property,
as the LS1043A PCIe controller also has some control registers in SCFG
block, while it has 3 controllers.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
---
V2:
- No change.
Documentation/devicetree/bindings/pci/layerscape-pci.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index 0033c898976e..4228562be505 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -33,7 +33,7 @@ Required properties:
"intr": The interrupt that is asserted for controller interrupts
- fsl,pcie-scfg: Must include two entries.
The first entry must be a link to the SCFG device node
- The second entry must be '0' or '1' based on physical PCIe controller index.
+ The second entry is the physical PCIe controller index starting from '0'.
This is used to get SCFG PEXN registers
- dma-coherent: Indicates that the hardware IP block can ensure the coherency
of the data transferred from/to the IP block. This can avoid the software
--
2.17.1
next prev parent reply other threads:[~2020-10-27 7:44 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-27 7:29 [PATCHv2 0/7] PCI: layerscape: Add power management support Zhiqiang Hou
2020-10-27 7:29 ` [PATCHv2 1/7] PCI: dwc: Fix a bug of the case dw_pci->ops is NULL Zhiqiang Hou
2020-10-27 7:29 ` [PATCHv2 2/7] PCI: layerscape: Change to use the DWC common link-up check function Zhiqiang Hou
2020-10-27 7:29 ` [PATCHv2 3/7] dt-bindings: pci: layerscape-pci: Add a optional property big-endian Zhiqiang Hou
2020-10-27 7:29 ` [PATCHv2 4/7] arm64: dts: layerscape: Add big-endian property for PCIe nodes Zhiqiang Hou
2020-10-27 7:29 ` Zhiqiang Hou [this message]
2020-10-27 7:30 ` [PATCHv2 6/7] arm64: dts: ls1043a: Add SCFG phandle " Zhiqiang Hou
2020-10-27 7:30 ` [PATCHv2 7/7] PCI: layerscape: Add power management support Zhiqiang Hou
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