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* [PATCH V2 0/2] Add support to configure DWC for ECRC
@ 2020-10-27  8:03 Vidya Sagar
  2020-10-27  8:03 ` [PATCH V2 1/2] PCI/AER: Add pcie_is_ecrc_enabled() API Vidya Sagar
  2020-10-27  8:03 ` [PATCH V2 2/2] PCI: dwc: Add support to configure for ECRC Vidya Sagar
  0 siblings, 2 replies; 6+ messages in thread
From: Vidya Sagar @ 2020-10-27  8:03 UTC (permalink / raw)
  To: jingoohan1, gustavo.pimentel, lorenzo.pieralisi, bhelgaas,
	amurray, robh, treding, jonathanh
  Cc: linux-pci, linux-kernel, kthota, mmaddireddy, vidyas, sagar.tv

This series has two patches.

Patch-1: Adds a public API to query if the system has ECRC policty turned on.

Patch-2: DesignWare core PCIe IP has a TLP Digest (TD) override bit in one of
its control registers of ATU. This bit needs to be programmed for proper ECRC
functionality. This is currently identified as an issue with DesignWare
IP version 4.90a. DWC code queries the PCIe sub-system through the API added
in Patch-1 to find out if ECRC is turned on or not and configures ATU
accordingly.

V2:
* Addressed Jingoo's review comments

Vidya Sagar (2):
  PCI/AER: Add pcie_is_ecrc_enabled() API
  PCI: dwc: Add support to configure for ECRC

 drivers/pci/controller/dwc/pcie-designware.c |  8 ++++++--
 drivers/pci/controller/dwc/pcie-designware.h |  1 +
 drivers/pci/pci.h                            |  2 ++
 drivers/pci/pcie/aer.c                       | 11 +++++++++++
 4 files changed, 20 insertions(+), 2 deletions(-)

-- 
2.17.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH V2 1/2] PCI/AER: Add pcie_is_ecrc_enabled() API
  2020-10-27  8:03 [PATCH V2 0/2] Add support to configure DWC for ECRC Vidya Sagar
@ 2020-10-27  8:03 ` Vidya Sagar
  2020-10-27 14:26   ` Jingoo Han
  2020-10-28  2:47   ` Ethan Zhao
  2020-10-27  8:03 ` [PATCH V2 2/2] PCI: dwc: Add support to configure for ECRC Vidya Sagar
  1 sibling, 2 replies; 6+ messages in thread
From: Vidya Sagar @ 2020-10-27  8:03 UTC (permalink / raw)
  To: jingoohan1, gustavo.pimentel, lorenzo.pieralisi, bhelgaas,
	amurray, robh, treding, jonathanh
  Cc: linux-pci, linux-kernel, kthota, mmaddireddy, vidyas, sagar.tv

Adds pcie_is_ecrc_enabled() API to let other sub-systems (like DesignWare)
to query if ECRC policy is enabled and perform any configuration
required in those respective sub-systems.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
V2:
* None from V1

 drivers/pci/pci.h      |  2 ++
 drivers/pci/pcie/aer.c | 11 +++++++++++
 2 files changed, 13 insertions(+)

diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index fa12f7cbc1a0..325fdbf91dde 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -575,9 +575,11 @@ static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
 #ifdef CONFIG_PCIE_ECRC
 void pcie_set_ecrc_checking(struct pci_dev *dev);
 void pcie_ecrc_get_policy(char *str);
+bool pcie_is_ecrc_enabled(void);
 #else
 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
 static inline void pcie_ecrc_get_policy(char *str) { }
+static inline bool pcie_is_ecrc_enabled(void) { return false; }
 #endif
 
 #ifdef CONFIG_PCIE_PTM
diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
index 65dff5f3457a..24363c895aba 100644
--- a/drivers/pci/pcie/aer.c
+++ b/drivers/pci/pcie/aer.c
@@ -207,6 +207,17 @@ void pcie_ecrc_get_policy(char *str)
 
 	ecrc_policy = i;
 }
+
+/**
+ * pcie_is_ecrc_enabled - returns if ECRC is enabled in the system or not
+ *
+ * Returns 1 if ECRC policy is enabled and 0 otherwise
+ */
+bool pcie_is_ecrc_enabled(void)
+{
+	return ecrc_policy == ECRC_POLICY_ON;
+}
+EXPORT_SYMBOL(pcie_is_ecrc_enabled);
 #endif	/* CONFIG_PCIE_ECRC */
 
 #define	PCI_EXP_AER_FLAGS	(PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | \
-- 
2.17.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH V2 2/2] PCI: dwc: Add support to configure for ECRC
  2020-10-27  8:03 [PATCH V2 0/2] Add support to configure DWC for ECRC Vidya Sagar
  2020-10-27  8:03 ` [PATCH V2 1/2] PCI/AER: Add pcie_is_ecrc_enabled() API Vidya Sagar
@ 2020-10-27  8:03 ` Vidya Sagar
  2020-10-27 14:24   ` Jingoo Han
  1 sibling, 1 reply; 6+ messages in thread
From: Vidya Sagar @ 2020-10-27  8:03 UTC (permalink / raw)
  To: jingoohan1, gustavo.pimentel, lorenzo.pieralisi, bhelgaas,
	amurray, robh, treding, jonathanh
  Cc: linux-pci, linux-kernel, kthota, mmaddireddy, vidyas, sagar.tv

DesignWare core has a TLP digest (TD) override bit in one of the control
registers of ATU. This bit also needs to be programmed for proper ECRC
functionality. This is currently identified as an issue with DesignWare
IP version 4.90a. This patch does the required programming in ATU upon
querying the system policy for ECRC.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
V2:
* Addressed Jingoo's review comment
* Removed saving 'td' bit information in 'dw_pcie' structure

 drivers/pci/controller/dwc/pcie-designware.c | 8 ++++++--
 drivers/pci/controller/dwc/pcie-designware.h | 1 +
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index b5e438b70cd5..cbd651b219d2 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -246,6 +246,8 @@ static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, u8 func_no,
 	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
 				 upper_32_bits(pci_addr));
 	val = type | PCIE_ATU_FUNC_NUM(func_no);
+	if (pci->version == 0x490A)
+		val = val | pcie_is_ecrc_enabled() << PCIE_ATU_TD_SHIFT;
 	val = upper_32_bits(size - 1) ?
 		val | PCIE_ATU_INCREASE_REGION_SIZE : val;
 	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, val);
@@ -294,8 +296,10 @@ static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
 			   lower_32_bits(pci_addr));
 	dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET,
 			   upper_32_bits(pci_addr));
-	dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type |
-			   PCIE_ATU_FUNC_NUM(func_no));
+	val = type | PCIE_ATU_FUNC_NUM(func_no);
+	if (pci->version == 0x490A)
+		val = val | pcie_is_ecrc_enabled() << PCIE_ATU_TD_SHIFT;
+	dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, val);
 	dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
 
 	/*
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 21dd06831b50..e5449b205c22 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -90,6 +90,7 @@
 #define PCIE_ATU_TYPE_IO		0x2
 #define PCIE_ATU_TYPE_CFG0		0x4
 #define PCIE_ATU_TYPE_CFG1		0x5
+#define PCIE_ATU_TD_SHIFT		8
 #define PCIE_ATU_FUNC_NUM(pf)           ((pf) << 20)
 #define PCIE_ATU_CR2			0x908
 #define PCIE_ATU_ENABLE			BIT(31)
-- 
2.17.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH V2 2/2] PCI: dwc: Add support to configure for ECRC
  2020-10-27  8:03 ` [PATCH V2 2/2] PCI: dwc: Add support to configure for ECRC Vidya Sagar
@ 2020-10-27 14:24   ` Jingoo Han
  0 siblings, 0 replies; 6+ messages in thread
From: Jingoo Han @ 2020-10-27 14:24 UTC (permalink / raw)
  To: Vidya Sagar, gustavo.pimentel, lorenzo.pieralisi, bhelgaas,
	amurray, robh, treding, jonathanh
  Cc: linux-pci, linux-kernel, kthota, mmaddireddy, sagar.tv, Han Jingoo

On 10/27/20, 4:03 AM, Vidya Sagar wrote:
> 
> DesignWare core has a TLP digest (TD) override bit in one of the control
> registers of ATU. This bit also needs to be programmed for proper ECRC
> functionality. This is currently identified as an issue with DesignWare
> IP version 4.90a. This patch does the required programming in ATU upon
> querying the system policy for ECRC.
>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>

Acked-by: Jingoo Han <jingoohan1@gmail.com>

Best regards,
Jingoo Han

> ---
> V2:
> * Addressed Jingoo's review comment
> * Removed saving 'td' bit information in 'dw_pcie' structure
>
>  drivers/pci/controller/dwc/pcie-designware.c | 8 ++++++--
>  drivers/pci/controller/dwc/pcie-designware.h | 1 +
>  2 files changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index b5e438b70cd5..cbd651b219d2 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -246,6 +246,8 @@ static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, u8 func_no,
>  	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
>  				 upper_32_bits(pci_addr));
>  	val = type | PCIE_ATU_FUNC_NUM(func_no);
> +	if (pci->version == 0x490A)
> +		val = val | pcie_is_ecrc_enabled() << PCIE_ATU_TD_SHIFT;
>  	val = upper_32_bits(size - 1) ?
>  		val | PCIE_ATU_INCREASE_REGION_SIZE : val;
>  	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, val);
> @@ -294,8 +296,10 @@ static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
>  			   lower_32_bits(pci_addr));
>  	dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET,
>  			   upper_32_bits(pci_addr));
> -	dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type |
> -			   PCIE_ATU_FUNC_NUM(func_no));
> +	val = type | PCIE_ATU_FUNC_NUM(func_no);
> +	if (pci->version == 0x490A)
> +		val = val | pcie_is_ecrc_enabled() << PCIE_ATU_TD_SHIFT;
> +	dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, val);
>  	dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
>
>  	/*
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 21dd06831b50..e5449b205c22 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -90,6 +90,7 @@
>  #define PCIE_ATU_TYPE_IO		0x2
>  #define PCIE_ATU_TYPE_CFG0		0x4
>  #define PCIE_ATU_TYPE_CFG1		0x5
> +#define PCIE_ATU_TD_SHIFT		8
>  #define PCIE_ATU_FUNC_NUM(pf)           ((pf) << 20)
>  #define PCIE_ATU_CR2			0x908
>  #define PCIE_ATU_ENABLE			BIT(31)
> -- 
> 2.17.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH V2 1/2] PCI/AER: Add pcie_is_ecrc_enabled() API
  2020-10-27  8:03 ` [PATCH V2 1/2] PCI/AER: Add pcie_is_ecrc_enabled() API Vidya Sagar
@ 2020-10-27 14:26   ` Jingoo Han
  2020-10-28  2:47   ` Ethan Zhao
  1 sibling, 0 replies; 6+ messages in thread
From: Jingoo Han @ 2020-10-27 14:26 UTC (permalink / raw)
  To: Vidya Sagar, gustavo.pimentel, lorenzo.pieralisi, bhelgaas,
	amurray, robh, treding, jonathanh
  Cc: linux-pci, linux-kernel, kthota, mmaddireddy, sagar.tv, Han Jingoo

On 10/27/20, 4:03 AM, Vidya Sagar wrote:
> 
> Adds pcie_is_ecrc_enabled() API to let other sub-systems (like DesignWare)
> to query if ECRC policy is enabled and perform any configuration
> required in those respective sub-systems.
>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>

Reviewed-by: Jingoo Han <jingoohan1@gmail.com>

Best regards,
Jingoo Han

> ---
> V2:
> * None from V1
>
>  drivers/pci/pci.h      |  2 ++
>  drivers/pci/pcie/aer.c | 11 +++++++++++
>  2 files changed, 13 insertions(+)
>
> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
> index fa12f7cbc1a0..325fdbf91dde 100644
> --- a/drivers/pci/pci.h
> +++ b/drivers/pci/pci.h
> @@ -575,9 +575,11 @@ static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
>  #ifdef CONFIG_PCIE_ECRC
>  void pcie_set_ecrc_checking(struct pci_dev *dev);
>  void pcie_ecrc_get_policy(char *str);
> +bool pcie_is_ecrc_enabled(void);
>  #else
>  static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
>  static inline void pcie_ecrc_get_policy(char *str) { }
> +static inline bool pcie_is_ecrc_enabled(void) { return false; }
>  #endif
>
>  #ifdef CONFIG_PCIE_PTM
> diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
> index 65dff5f3457a..24363c895aba 100644
> --- a/drivers/pci/pcie/aer.c
> +++ b/drivers/pci/pcie/aer.c
> @@ -207,6 +207,17 @@ void pcie_ecrc_get_policy(char *str)
>
>  	ecrc_policy = i;
>  }
> +
> +/**
> + * pcie_is_ecrc_enabled - returns if ECRC is enabled in the system or not
> + *
> + * Returns 1 if ECRC policy is enabled and 0 otherwise
> + */
> +bool pcie_is_ecrc_enabled(void)
> +{
> +	return ecrc_policy == ECRC_POLICY_ON;
> +}
> +EXPORT_SYMBOL(pcie_is_ecrc_enabled);
>  #endif	/* CONFIG_PCIE_ECRC */
>
>  #define	PCI_EXP_AER_FLAGS	(PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | \
> -- 
> 2.17.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH V2 1/2] PCI/AER: Add pcie_is_ecrc_enabled() API
  2020-10-27  8:03 ` [PATCH V2 1/2] PCI/AER: Add pcie_is_ecrc_enabled() API Vidya Sagar
  2020-10-27 14:26   ` Jingoo Han
@ 2020-10-28  2:47   ` Ethan Zhao
  1 sibling, 0 replies; 6+ messages in thread
From: Ethan Zhao @ 2020-10-28  2:47 UTC (permalink / raw)
  To: Vidya Sagar
  Cc: jingoohan1, gustavo.pimentel, lorenzo.pieralisi, Bjorn Helgaas,
	amurray, robh, treding, jonathanh, linux-pci,
	Linux Kernel Mailing List, kthota, mmaddireddy, sagar.tv

On Wed, Oct 28, 2020 at 9:48 AM Vidya Sagar <vidyas@nvidia.com> wrote:
>
> Adds pcie_is_ecrc_enabled() API to let other sub-systems (like DesignWare)
> to query if ECRC policy is enabled and perform any configuration
> required in those respective sub-systems.
>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> ---
> V2:
> * None from V1
>
>  drivers/pci/pci.h      |  2 ++
>  drivers/pci/pcie/aer.c | 11 +++++++++++
>  2 files changed, 13 insertions(+)
>
> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
> index fa12f7cbc1a0..325fdbf91dde 100644
> --- a/drivers/pci/pci.h
> +++ b/drivers/pci/pci.h
> @@ -575,9 +575,11 @@ static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
>  #ifdef CONFIG_PCIE_ECRC
>  void pcie_set_ecrc_checking(struct pci_dev *dev);
>  void pcie_ecrc_get_policy(char *str);
> +bool pcie_is_ecrc_enabled(void);
>  #else
>  static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
>  static inline void pcie_ecrc_get_policy(char *str) { }
> +static inline bool pcie_is_ecrc_enabled(void) { return false; }
>  #endif
>
>  #ifdef CONFIG_PCIE_PTM
> diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
> index 65dff5f3457a..24363c895aba 100644
> --- a/drivers/pci/pcie/aer.c
> +++ b/drivers/pci/pcie/aer.c
> @@ -207,6 +207,17 @@ void pcie_ecrc_get_policy(char *str)
>
>         ecrc_policy = i;
>  }
> +
> +/**
> + * pcie_is_ecrc_enabled - returns if ECRC is enabled in the system or not
> + *
> + * Returns 1 if ECRC policy is enabled and 0 otherwise
 How about 'Returns true if ECRC policy is enabled and false otherwise'  ?
> + */
> +bool pcie_is_ecrc_enabled(void)
> +{
> +       return ecrc_policy == ECRC_POLICY_ON;
> +}
> +EXPORT_SYMBOL(pcie_is_ecrc_enabled);
>  #endif /* CONFIG_PCIE_ECRC */
>
>  #define        PCI_EXP_AER_FLAGS       (PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | \
> --
> 2.17.1
>

^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, back to index

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-10-27  8:03 [PATCH V2 0/2] Add support to configure DWC for ECRC Vidya Sagar
2020-10-27  8:03 ` [PATCH V2 1/2] PCI/AER: Add pcie_is_ecrc_enabled() API Vidya Sagar
2020-10-27 14:26   ` Jingoo Han
2020-10-28  2:47   ` Ethan Zhao
2020-10-27  8:03 ` [PATCH V2 2/2] PCI: dwc: Add support to configure for ECRC Vidya Sagar
2020-10-27 14:24   ` Jingoo Han

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