From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2C17C00A89 for ; Mon, 2 Nov 2020 10:12:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6177B222E8 for ; Mon, 2 Nov 2020 10:12:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="fHL7+C0F" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728475AbgKBKMg (ORCPT ); Mon, 2 Nov 2020 05:12:36 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:39250 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728464AbgKBKMf (ORCPT ); Mon, 2 Nov 2020 05:12:35 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0A2ACSPK012582; Mon, 2 Nov 2020 04:12:28 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1604311948; bh=VwsFBA0ieDn50BfS5Y1sE5jJ3zG5NZYGHo75lDjg+oY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=fHL7+C0FFMAL66arLR1VmSlyGPh2D6zDil+jDxn+PjqdJ2hmIveAhK9jvHaYr/yfZ tftypxYkXb14pSzB95G0vNfaH56J2ae+5neGj6Y9xURs4KPAOKBcWFXKirnTyRxQXe MzwjFGp3QToFrWNIOmZ6xQJfUpR3LgqxmqJXPGzo= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0A2ACRx2067878 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 2 Nov 2020 04:12:27 -0600 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 2 Nov 2020 04:12:04 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 2 Nov 2020 04:12:04 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0A2ABtuY059084; Mon, 2 Nov 2020 04:12:01 -0600 From: Kishon Vijay Abraham I To: Lee Jones , Rob Herring , Bjorn Helgaas , Tero Kristo , Nishanth Menon CC: Roger Quadros , , , , Subject: [PATCH 1/8] dt-bindings: mfd: ti,j721e-system-controller.yaml: Document "pcie-ctrl" Date: Mon, 2 Nov 2020 15:41:47 +0530 Message-ID: <20201102101154.13598-2-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201102101154.13598-1-kishon@ti.com> References: <20201102101154.13598-1-kishon@ti.com> MIME-Version: 1.0 Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add binding documentation for "pcie-ctrl" which should be a subnode of the system controller. Signed-off-by: Kishon Vijay Abraham I --- .../devicetree/bindings/mfd/ti,j721e-system-controller.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml index 19fcf59fd2fe..fd985794e419 100644 --- a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml +++ b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml @@ -50,6 +50,12 @@ patternProperties: specified in Documentation/devicetree/bindings/mux/reg-mux.txt + "^pcie-ctrl@[0-9a-f]+$": + type: object + description: | + This is the PCIe controller configuration required to configre PCIe + mode, lane width and speed. + required: - compatible - reg -- 2.17.1