linux-pci.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Nishanth Menon <nm@ti.com>
To: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Lee Jones <lee.jones@linaro.org>,
	Rob Herring <robh+dt@kernel.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Tero Kristo <t-kristo@ti.com>, Roger Quadros <rogerq@ti.com>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-pci@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 8/8] arm64: dts: ti: k3-j721e-main: Fix PCIe maximum outbound regions
Date: Mon, 2 Nov 2020 10:41:37 -0600	[thread overview]
Message-ID: <20201102164137.ntl3v6gu274ek2r2@gauze> (raw)
In-Reply-To: <20201102101154.13598-9-kishon@ti.com>

On 15:41-20201102, Kishon Vijay Abraham I wrote:
> PCIe controller in J721E supports a maximum of 32 outbound regions.
> commit 4e5833884f66 ("arm64: dts: ti: k3-j721e-main: Add PCIe device tree
> nodes") incorrectly added maximum number of outbound regions to 16. Fix
> it here.
> 
> Fixes: 4e5833884f66 ("arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes")
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> index e2a96b2c423c..61b533130ed1 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> @@ -652,7 +652,7 @@
>  		power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
>  		clocks = <&k3_clks 239 1>;
>  		clock-names = "fck";
> -		cdns,max-outbound-regions = <16>;
> +		cdns,max-outbound-regions = <32>;
>  		max-functions = /bits/ 8 <6>;
>  		max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
>  		dma-coherent;
> @@ -701,7 +701,7 @@
>  		power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
>  		clocks = <&k3_clks 240 1>;
>  		clock-names = "fck";
> -		cdns,max-outbound-regions = <16>;
> +		cdns,max-outbound-regions = <32>;
>  		max-functions = /bits/ 8 <6>;
>  		max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
>  		dma-coherent;
> @@ -750,7 +750,7 @@
>  		power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
>  		clocks = <&k3_clks 241 1>;
>  		clock-names = "fck";
> -		cdns,max-outbound-regions = <16>;
> +		cdns,max-outbound-regions = <32>;
>  		max-functions = /bits/ 8 <6>;
>  		max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
>  		dma-coherent;
> @@ -799,7 +799,7 @@
>  		power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
>  		clocks = <&k3_clks 242 1>;
>  		clock-names = "fck";
> -		cdns,max-outbound-regions = <16>;
> +		cdns,max-outbound-regions = <32>;
>  		max-functions = /bits/ 8 <6>;
>  		max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
>  		dma-coherent;
> -- 
> 2.17.1
> 

Does this need to be part of this series? If NOT, please pull this  out
and repost so that it can be independently picked up since there is no
dependency on the bindings or any part of this series?


-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

  reply	other threads:[~2020-11-02 16:42 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-02 10:11 [PATCH 0/8] J7200: Add PCIe DT nodes to Enable PCIe Kishon Vijay Abraham I
2020-11-02 10:11 ` [PATCH 1/8] dt-bindings: mfd: ti,j721e-system-controller.yaml: Document "pcie-ctrl" Kishon Vijay Abraham I
2020-11-05 16:54   ` Rob Herring
2020-11-09 14:17     ` Kishon Vijay Abraham I
2020-11-02 10:11 ` [PATCH 2/8] dt-bindings: PCI: Add host mode dt-bindings for TI's J7200 SoC Kishon Vijay Abraham I
2020-11-05 16:56   ` Rob Herring
2020-11-02 10:11 ` [PATCH 3/8] dt-bindings: PCI: Add EP " Kishon Vijay Abraham I
2020-11-05 16:56   ` Rob Herring
2020-11-02 10:11 ` [PATCH 4/8] arm64: dts: ti: k3-j7200-main: Add DT for WIZ and SERDES Kishon Vijay Abraham I
2020-11-02 10:11 ` [PATCH 5/8] arm64: dts: ti: k3-j7200-main: Add PCIe device tree node Kishon Vijay Abraham I
2020-11-02 10:11 ` [PATCH 6/8] arm64: dts: ti: k3-j7200-common-proc-board: Enable SERDES0 Kishon Vijay Abraham I
2020-11-02 10:11 ` [PATCH 7/8] arm64: dts: ti: k3-j7200-common-proc-board: Enable PCIe Kishon Vijay Abraham I
2020-11-02 10:11 ` [PATCH 8/8] arm64: dts: ti: k3-j721e-main: Fix PCIe maximum outbound regions Kishon Vijay Abraham I
2020-11-02 16:41   ` Nishanth Menon [this message]
2020-11-03  2:18     ` Kishon Vijay Abraham I
2020-11-05 16:53     ` Rob Herring
2020-11-06 15:10       ` Kishon Vijay Abraham I

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20201102164137.ntl3v6gu274ek2r2@gauze \
    --to=nm@ti.com \
    --cc=bhelgaas@google.com \
    --cc=devicetree@vger.kernel.org \
    --cc=kishon@ti.com \
    --cc=lee.jones@linaro.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=robh+dt@kernel.org \
    --cc=rogerq@ti.com \
    --cc=t-kristo@ti.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).