From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C87EC4741F for ; Sun, 8 Nov 2020 23:37:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 00914206DC for ; Sun, 8 Nov 2020 23:37:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728006AbgKHXhC (ORCPT ); Sun, 8 Nov 2020 18:37:02 -0500 Received: from mga06.intel.com ([134.134.136.31]:22852 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727929AbgKHXhC (ORCPT ); Sun, 8 Nov 2020 18:37:02 -0500 IronPort-SDR: cZ/S+B8Ys5Au9VeJwWnNan44+9dBZvDkQyu6pcjQhfD304Uu6fl66EioyGoz3zYnJFoPVx+CN0 4I5AAAx+EZbw== X-IronPort-AV: E=McAfee;i="6000,8403,9799"; a="231363247" X-IronPort-AV: E=Sophos;i="5.77,462,1596524400"; d="scan'208";a="231363247" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Nov 2020 15:37:01 -0800 IronPort-SDR: FxN8RtMIMMuInYkQifgTBpuGLs0DPi9bCPJXW0oQzPboOaY1UDDmLAeN6+FkXJ9LaGRFc1kjo2 Gl+nen5Naaog== X-IronPort-AV: E=Sophos;i="5.77,462,1596524400"; d="scan'208";a="540604292" Received: from araj-mobl1.jf.intel.com ([10.255.228.179]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Nov 2020 15:37:00 -0800 Date: Sun, 8 Nov 2020 15:36:59 -0800 From: "Raj, Ashok" To: Jason Gunthorpe Cc: Thomas Gleixner , Dan Williams , "Tian, Kevin" , "Jiang, Dave" , Bjorn Helgaas , "vkoul@kernel.org" , "Dey, Megha" , "maz@kernel.org" , "bhelgaas@google.com" , "alex.williamson@redhat.com" , "Pan, Jacob jun" , "Liu, Yi L" , "Lu, Baolu" , "Kumar, Sanjay K" , "Luck, Tony" , "jing.lin@intel.com" , "kwankhede@nvidia.com" , "eric.auger@redhat.com" , "parav@mellanox.com" , "rafael@kernel.org" , "netanelg@mellanox.com" , "shahafs@mellanox.com" , "yan.y.zhao@linux.intel.com" , "pbonzini@redhat.com" , "Ortiz, Samuel" , "Hossain, Mona" , "dmaengine@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-pci@vger.kernel.org" , "kvm@vger.kernel.org" , Ashok Raj Subject: Re: [PATCH v4 06/17] PCI: add SIOV and IMS capability detection Message-ID: <20201108233659.GB32074@araj-mobl1.jf.intel.com> References: <20201104135415.GX2620339@nvidia.com> <20201106131415.GT2620339@nvidia.com> <20201106164850.GA85879@otc-nc-03> <20201106175131.GW2620339@nvidia.com> <20201107001207.GA2620339@nvidia.com> <87pn4nk7nn.fsf@nanos.tec.linutronix.de> <20201108232341.GB2620339@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20201108232341.GB2620339@nvidia.com> User-Agent: Mutt/1.9.1 (2017-09-22) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Hi Jason, On Sun, Nov 08, 2020 at 07:23:41PM -0400, Jason Gunthorpe wrote: > > IDXD is worring about case #4, I think, but I didn't follow in that > whole discussion about the IMS table layout if they PASID tag the IMS > MemWr or not?? Ashok can you clarify? > The PASID in the interrupt store is for the IDXD to verify the interrupt handle that came with the ENQCMD. User applications can obtain an interrupt handle and ask for interrupt to be generated for transactions submitted via ENQCMD. IDXD will compare the PASID that came with ENQCMD and verify if the PASID matches the one stored in the Interrupt Table before generating the MemWr. So MemWr for interrupts remains unchanged for IDXD on the wire. PASID is present in interrupt store because the value was programmed by user space, and needs OS/hardware to ensure the entity asking for interrupts has ownership for the interrupt handle.