From: Kishon Vijay Abraham I <kishon@ti.com>
To: Tero Kristo <t-kristo@ti.com>, Nishanth Menon <nm@ti.com>,
Rob Herring <robh+dt@kernel.org>, Roger Quadros <rogerq@ti.com>,
Lee Jones <lee.jones@linaro.org>
Cc: Kishon Vijay Abraham I <kishon@ti.com>,
<linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>, Bjorn Helgaas <bhelgaas@google.com>,
<linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH v2 4/7] arm64: dts: ti: k3-j7200-main: Add DT for WIZ and SERDES
Date: Mon, 9 Nov 2020 22:34:06 +0530 [thread overview]
Message-ID: <20201109170409.4498-5-kishon@ti.com> (raw)
In-Reply-To: <20201109170409.4498-1-kishon@ti.com>
Add dt node for the single instance of WIZ and SERDES module
shared by PCIe, CPSW (SGMII/QSGMII) and USB.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 61 +++++++++++++++++++++++
1 file changed, 61 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 72d6496e88dd..7668404c178b 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -417,6 +417,67 @@
dma-coherent;
};
+ serdes_refclk: serdes_refclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
+ serdes_wiz0: wiz@5060000 {
+ compatible = "ti,j721e-wiz-10g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ num-lanes = <4>;
+ #reset-cells = <1>;
+ ranges = <0x5060000 0x0 0x5060000 0x10000>;
+
+ assigned-clocks = <&k3_clks 292 85>;
+ assigned-clock-parents = <&k3_clks 292 89>;
+
+ wiz0_pll0_refclk: pll0-refclk {
+ clocks = <&k3_clks 292 85>, <&serdes_refclk>;
+ clock-output-names = "wiz0_pll0_refclk";
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz0_pll0_refclk>;
+ assigned-clock-parents = <&k3_clks 292 85>;
+ };
+
+ wiz0_pll1_refclk: pll1-refclk {
+ clocks = <&k3_clks 292 85>, <&serdes_refclk>;
+ clock-output-names = "wiz0_pll1_refclk";
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz0_pll1_refclk>;
+ assigned-clock-parents = <&k3_clks 292 85>;
+ };
+
+ wiz0_refclk_dig: refclk-dig {
+ clocks = <&k3_clks 292 85>, <&serdes_refclk>;
+ clock-output-names = "wiz0_refclk_dig";
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz0_refclk_dig>;
+ assigned-clock-parents = <&k3_clks 292 85>;
+ };
+
+ wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
+ clocks = <&wiz0_refclk_dig>;
+ #clock-cells = <0>;
+ };
+
+ serdes0: serdes@5060000 {
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x05060000 0x00010000>;
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz0 0>;
+ reset-names = "torrent_reset";
+ clocks = <&wiz0_pll0_refclk>;
+ clock-names = "refclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
usbss0: cdns-usb@4104000 {
compatible = "ti,j721e-usb";
reg = <0x00 0x4104000 0x00 0x100>;
--
2.17.1
next prev parent reply other threads:[~2020-11-09 17:04 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-09 17:04 [PATCH v2 0/7] J7200: Add PCIe DT nodes to Enable PCIe Kishon Vijay Abraham I
2020-11-09 17:04 ` [PATCH v2 1/7] dt-bindings: mfd: ti,j721e-system-controller.yaml: Document "syscon" Kishon Vijay Abraham I
2020-11-11 21:28 ` Rob Herring
2020-11-12 5:25 ` Kishon Vijay Abraham I
2020-11-12 16:46 ` Rob Herring
2020-11-09 17:04 ` [PATCH v2 2/7] dt-bindings: PCI: Add host mode dt-bindings for TI's J7200 SoC Kishon Vijay Abraham I
2020-11-09 17:04 ` [PATCH v2 3/7] dt-bindings: PCI: Add EP " Kishon Vijay Abraham I
2020-11-09 17:04 ` Kishon Vijay Abraham I [this message]
2020-11-09 17:04 ` [PATCH v2 5/7] arm64: dts: ti: k3-j7200-main: Add PCIe device tree node Kishon Vijay Abraham I
2020-11-12 16:05 ` Vignesh Raghavendra
2020-11-09 17:04 ` [PATCH v2 6/7] arm64: dts: ti: k3-j7200-common-proc-board: Enable SERDES0 Kishon Vijay Abraham I
2020-11-12 15:58 ` Vignesh Raghavendra
2020-11-09 17:04 ` [PATCH v2 7/7] arm64: dts: ti: k3-j7200-common-proc-board: Enable PCIe Kishon Vijay Abraham I
2020-11-12 15:56 ` Vignesh Raghavendra
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