Re: [PATCH v2 2/2] PCI: keembay: Add support for Intel Keem Bay

From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
Cc: bhelgaas@google.com, robh+dt@kernel.org,
	lorenzo.pieralisi@arm.com, linux-pci@vger.kernel.org,
	devicetree@vger.kernel.org, mgross@linux.intel.com,
	lakshmi.bai.raja.subramanian@intel.com
Subject: Re: [PATCH v2 2/2] PCI: keembay: Add support for Intel Keem Bay
Date: Wed, 25 Nov 2020 14:50:23 +0200	[thread overview]
Message-ID: <20201125125023.GS4077@smile.fi.intel.com> (raw)
In-Reply-To: <20201125101152.5326-3-wan.ahmad.zainie.wan.mohamad@intel.com>

On Wed, Nov 25, 2020 at 06:11:52PM +0800, Wan Ahmad Zainie wrote:
> Add driver for Intel Keem Bay SoC PCIe controller. This controller
> is based on DesignWare PCIe core.
> 
> In root complex mode, only internal reference clock is possible for
> Keem Bay A0. For Keem Bay B0, external reference clock can be used
> and will be the default configuration. Currently, keembay_pcie_of_data
> structure has one member. It will be expanded later to handle this
> difference.
> 
> Endpoint mode link initialization is handled by the boot firmware.

...

> +	switch (pcie->mode) {
> +	case DW_PCIE_RC_TYPE:
> +		if (!IS_ENABLED(CONFIG_PCIE_KEEMBAY_HOST))
> +			return -ENODEV;
> +

> +		ret = keembay_pcie_add_pcie_port(pcie, pdev);
> +		if (ret < 0)
> +			return ret;
> +		break;

		return keembay_pcie_add_pcie_port(pcie, pdev);

> +	case DW_PCIE_EP_TYPE:
> +		if (!IS_ENABLED(CONFIG_PCIE_KEEMBAY_EP))
> +			return -ENODEV;
> +
> +		pci->ep.ops = &keembay_pcie_ep_ops;
> +		return dw_pcie_ep_init(&pci->ep);
> +	default:
> +		dev_err(dev, "Invalid device type %d\n", pcie->mode);
> +		return -ENODEV;
> +	}

> +	return 0;

...and drop this one.

> +}

-- 
With Best Regards,
Andy Shevchenko