[PATCH 0/2] brcmstb: initial work on BCM4908

[PATCH 0/2] brcmstb: initial work on BCM4908

[Rafał Miłecki]

From: Rafał Miłecki <rafal@milecki.pl>

BCM4908 uses very similar hardware to the STB one. It still requires
some tweaks but this initial work allows accessing hardware without:

Internal error: synchronous external abort: 96000210 [#1] PREEMPT SMP                                                                                                                                                                                                          

Rafał Miłecki (2):
  dt-bindings: PCI: brcmstb: add BCM4908 binding
  PCI: brcmstb: support BCM4908 with external PERST# signal controller

 .../bindings/pci/brcm,stb-pcie.yaml           | 30 +++++++++++++++--
 drivers/pci/controller/Kconfig                |  2 +-
 drivers/pci/controller/pcie-brcmstb.c         | 33 +++++++++++++++++--
 3 files changed, 60 insertions(+), 5 deletions(-)

-- 
2.26.2

[PATCH 1/2] dt-bindings: PCI: brcmstb: add BCM4908 binding

[Rafał Miłecki]

From: Rafał Miłecki <rafal@milecki.pl>

BCM4908 is a SoC family with PCIe controller sharing design with the one
for STB. BCM4908 has different power management and memory controller so
few tweaks are required.

PERST# signal on BCM4908 is handled by an external MISC block so it
needs specifying a reset phandle.

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
---
 .../bindings/pci/brcm,stb-pcie.yaml           | 30 +++++++++++++++++--
 1 file changed, 28 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
index 807694b4f41f..d3ab9e22f97c 100644
--- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
@@ -14,6 +14,7 @@ properties:
     items:
       - enum:
           - brcm,bcm2711-pcie # The Raspberry Pi 4
+          - brcm,bcm4908-pcie
           - brcm,bcm7211-pcie # Broadcom STB version of RPi4
           - brcm,bcm7278-pcie # Broadcom 7278 Arm
           - brcm,bcm7216-pcie # Broadcom 7216 Arm
@@ -64,8 +65,6 @@ properties:
   aspm-no-l0s: true
 
   resets:
-    description: for "brcm,bcm7216-pcie", must be a valid reset
-      phandle pointing to the RESCAL reset controller provider node.
     $ref: "/schemas/types.yaml#/definitions/phandle"
 
   reset-names:
@@ -98,12 +97,39 @@ required:
 
 allOf:
   - $ref: /schemas/pci/pci-bus.yaml#
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: brcm,bcm4908-pcie
+    then:
+      properties:
+        resets:
+          items:
+            - description: reset controller handling the PERST# signal
+
+        reset-names:
+          items:
+            - const: perst
+
+      required:
+        - resets
+        - reset-names
   - if:
       properties:
         compatible:
           contains:
             const: brcm,bcm7216-pcie
     then:
+      properties:
+        resets:
+          items:
+            - description: phandle pointing to the RESCAL reset controller
+
+        reset-names:
+          items:
+            - const: rescal
+
       required:
         - resets
         - reset-names
-- 
2.26.2

[PATCH 2/2] PCI: brcmstb: support BCM4908 with external PERST# signal controller

[Rafał Miłecki]

From: Rafał Miłecki <rafal@milecki.pl>

BCM4908 uses external MISC block for controlling PERST# signal. Use it
as a reset controller.

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
---
 drivers/pci/controller/Kconfig        |  2 +-
 drivers/pci/controller/pcie-brcmstb.c | 33 +++++++++++++++++++++++++--
 2 files changed, 32 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 64e2f5e379aa..d44c70bb88f6 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -273,7 +273,7 @@ config VMD
 
 config PCIE_BRCMSTB
 	tristate "Broadcom Brcmstb PCIe host controller"
-	depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST
+	depends on ARCH_BRCMSTB || ARCH_BCM2835 || ARCH_BCM4908 || COMPILE_TEST
 	depends on OF
 	depends on PCI_MSI_IRQ_DOMAIN
 	default ARCH_BRCMSTB
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index 9c3d2982248d..10023da323d5 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -96,6 +96,7 @@
 
 #define PCIE_MISC_REVISION				0x406c
 #define  BRCM_PCIE_HW_REV_33				0x0303
+#define  BRCM_PCIE_HW_REV_3_20				0x0320
 
 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT		0x4070
 #define  PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK	0xfff00000
@@ -190,6 +191,7 @@
 struct brcm_pcie;
 static inline void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val);
 static inline void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val);
+static inline void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val);
 static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val);
 static inline void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val);
 
@@ -205,6 +207,7 @@ enum {
 };
 
 enum pcie_type {
+	BCM4908,
 	GENERIC,
 	BCM7278,
 	BCM2711,
@@ -230,6 +233,13 @@ static const struct pcie_cfg_data generic_cfg = {
 	.bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
 };
 
+static const struct pcie_cfg_data bcm4908_cfg = {
+	.offsets	= pcie_offsets,
+	.type		= BCM4908,
+	.perst_set	= brcm_pcie_perst_set_4908,
+	.bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
+};
+
 static const int pcie_offset_bcm7278[] = {
 	[RGR1_SW_INIT_1] = 0xc010,
 	[EXT_CFG_INDEX] = 0x9000,
@@ -282,6 +292,7 @@ struct brcm_pcie {
 	const int		*reg_offsets;
 	enum pcie_type		type;
 	struct reset_control	*rescal;
+	struct reset_control	*perst_reset;
 	int			num_memc;
 	u64			memc_size[PCIE_BRCM_MAX_MEMC];
 	u32			hw_rev;
@@ -747,6 +758,18 @@ static inline void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32
 	writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
 }
 
+static inline void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val)
+{
+	if (WARN_ONCE(!pcie->perst_reset, "missing PERST# reset controller\n") ||
+	    WARN_ONCE(pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20, "unsupported hardware revision\n"))
+		return;
+
+	if (val)
+		reset_control_assert(pcie->perst_reset);
+	else
+		reset_control_deassert(pcie->perst_reset);
+}
+
 static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val)
 {
 	u32 tmp;
@@ -1206,6 +1229,7 @@ static int brcm_pcie_remove(struct platform_device *pdev)
 
 static const struct of_device_id brcm_pcie_match[] = {
 	{ .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
+	{ .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg },
 	{ .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg },
 	{ .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
 	{ .compatible = "brcm,bcm7216-pcie", .data = &bcm7278_cfg },
@@ -1262,11 +1286,18 @@ static int brcm_pcie_probe(struct platform_device *pdev)
 		clk_disable_unprepare(pcie->clk);
 		return PTR_ERR(pcie->rescal);
 	}
+	pcie->perst_reset = devm_reset_control_get_optional_shared(&pdev->dev, "perst");
+	if (IS_ERR(pcie->perst_reset)) {
+		clk_disable_unprepare(pcie->clk);
+		return PTR_ERR(pcie->perst_reset);
+	}
 
 	ret = reset_control_deassert(pcie->rescal);
 	if (ret)
 		dev_err(&pdev->dev, "failed to deassert 'rescal'\n");
 
+	pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION);
+
 	ret = brcm_phy_start(pcie);
 	if (ret) {
 		reset_control_assert(pcie->rescal);
@@ -1278,8 +1309,6 @@ static int brcm_pcie_probe(struct platform_device *pdev)
 	if (ret)
 		goto fail;
 
-	pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION);
-
 	msi_np = of_parse_phandle(pcie->np, "msi-parent", 0);
 	if (pci_msi_enabled() && msi_np == pcie->np) {
 		ret = brcm_pcie_enable_msi(pcie);
-- 
2.26.2

Re: [PATCH 1/2] dt-bindings: PCI: brcmstb: add BCM4908 binding

[Florian Fainelli]

On 11/26/2020 5:59 AM, Rafał Miłecki wrote:
> From: Rafał Miłecki <rafal@milecki.pl>
> 
> BCM4908 is a SoC family with PCIe controller sharing design with the one
> for STB. BCM4908 has different power management and memory controller so
> few tweaks are required.
> 
> PERST# signal on BCM4908 is handled by an external MISC block so it
> needs specifying a reset phandle.
> 
> Signed-off-by: Rafał Miłecki <rafal@milecki.pl>

Acked-by: Florian Fainelli <f.fainelli@gmail.com>
-- 
Florian

Re: [PATCH 2/2] PCI: brcmstb: support BCM4908 with external PERST# signal controller

[Florian Fainelli]

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On 11/26/2020 5:59 AM, Rafał Miłecki wrote:
> From: Rafał Miłecki <rafal@milecki.pl>
> 
> BCM4908 uses external MISC block for controlling PERST# signal. Use it
> as a reset controller.
> 
> Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
> ---

>  enum pcie_type {
> +	BCM4908,
>  	GENERIC,

This needs to be moved after GENERIC such that GENERIC == 0

>  	BCM7278,
>  	BCM2711,
> @@ -230,6 +233,13 @@ static const struct pcie_cfg_data generic_cfg = {
>  	.bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
>  };
>  
> +static const struct pcie_cfg_data bcm4908_cfg = {
> +	.offsets	= pcie_offsets,
> +	.type		= BCM4908,
> +	.perst_set	= brcm_pcie_perst_set_4908,
> +	.bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
> +};
> +
>  static const int pcie_offset_bcm7278[] = {
>  	[RGR1_SW_INIT_1] = 0xc010,
>  	[EXT_CFG_INDEX] = 0x9000,
> @@ -282,6 +292,7 @@ struct brcm_pcie {
>  	const int		*reg_offsets;
>  	enum pcie_type		type;
>  	struct reset_control	*rescal;
> +	struct reset_control	*perst_reset;
>  	int			num_memc;
>  	u64			memc_size[PCIE_BRCM_MAX_MEMC];
>  	u32			hw_rev;
> @@ -747,6 +758,18 @@ static inline void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32
>  	writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
>  }
>  
> +static inline void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val)
> +{
> +	if (WARN_ONCE(!pcie->perst_reset, "missing PERST# reset controller\n") ||
> +	    WARN_ONCE(pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20, "unsupported hardware revision\n"))
> +		return;
> +
> +	if (val)
> +		reset_control_assert(pcie->perst_reset);
> +	else
> +		reset_control_deassert(pcie->perst_reset);
> +}
> +
>  static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val)
>  {
>  	u32 tmp;
> @@ -1206,6 +1229,7 @@ static int brcm_pcie_remove(struct platform_device *pdev)
>  
>  static const struct of_device_id brcm_pcie_match[] = {
>  	{ .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
> +	{ .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg },
>  	{ .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg },
>  	{ .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
>  	{ .compatible = "brcm,bcm7216-pcie", .data = &bcm7278_cfg },
> @@ -1262,11 +1286,18 @@ static int brcm_pcie_probe(struct platform_device *pdev)
>  		clk_disable_unprepare(pcie->clk);
>  		return PTR_ERR(pcie->rescal);
>  	}
> +	pcie->perst_reset = devm_reset_control_get_optional_shared(&pdev->dev, "perst");

Is not this an exclusive reset?

> +	if (IS_ERR(pcie->perst_reset)) {
> +		clk_disable_unprepare(pcie->clk);
> +		return PTR_ERR(pcie->perst_reset);
> +	}
>  
>  	ret = reset_control_deassert(pcie->rescal);
>  	if (ret)
>  		dev_err(&pdev->dev, "failed to deassert 'rescal'\n");
>  
> +	pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION);

This is likely going to cause a regression on STB, you cannot read from
most PCIe registers except the main bridge register until after
brcm_pcie_setup() has been called. I do not find the warning on an
unknown revision to be particularly helpful, can you consider leaving
the hw_rev read where it is and not warn?
-- 
Florian

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