From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77A78C71155 for ; Sun, 29 Nov 2020 23:08:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4F4A62224A for ; Sun, 29 Nov 2020 23:08:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727691AbgK2XId (ORCPT ); Sun, 29 Nov 2020 18:08:33 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:44538 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726304AbgK2XId (ORCPT ); Sun, 29 Nov 2020 18:08:33 -0500 Received: by mail-wr1-f68.google.com with SMTP id 64so13064696wra.11 for ; Sun, 29 Nov 2020 15:08:16 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=w7DrLBT8KBYKfbvtR7994XDirbE4jnXzlQLSoJlL9lc=; b=Z14E7mDO1eaRmbZRdiA2D93K66tckvBISHxzDbVb6Z/uL59Ueb+JqDs47RIkbng6Tq MLSoR8ZiCX505+I1qvKSK+czeLoK3nUQg/xeagijmEF//SuVyRmYIdCajQQqwwB1fs1/ aB8nxWwzoPsArDFoNIDhC2newJjn/VHM8rGhrCRbAI4oneCzWDl8y4P/JsCaYDgK+ejs GxHt7LZ1e4z4GndWNKipwVIE6r53PJQMlUtimDL1PfnPoT4/ABPpeZaqzUPq+ZlX9yfc 1XP+07+Wmy6SxJT6DLEId5Ta3oNO8JT7l3TG0XXy7rQpTccNNEvpPSnN3LVoUJLjM8Vy Yf4w== X-Gm-Message-State: AOAM530+Ud6ySUKsS0FLTcNTDwvFQTzYHDpFZUQ9buGcSc1qqPEzTWYB TKFQE+5X1qfZccoBJZ9EP74= X-Google-Smtp-Source: ABdhPJwdjGj7iDsGU1B5WR1LxkaOGB+ic6Eu0jtLWAlHXS2/EdXYuqT/jY33YywMRM935NcuXWVL6A== X-Received: by 2002:a5d:65ca:: with SMTP id e10mr24605112wrw.42.1606691270924; Sun, 29 Nov 2020 15:07:50 -0800 (PST) Received: from workstation.lan ([95.155.85.46]) by smtp.gmail.com with ESMTPSA id d2sm24831005wrn.43.2020.11.29.15.07.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Nov 2020 15:07:50 -0800 (PST) From: =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= To: Bjorn Helgaas Cc: Rob Herring , Jonathan Cameron , Jonathan Chocron , Shawn Lin , Heiko Stuebner , Zhou Wang , Lorenzo Pieralisi , Will Deacon , Robert Richter , Michal Simek , Toan Le , Michael Ellerman , Benjamin Herrenschmidt , Paul Mackerras , Thomas Petazzoni , Nicolas Saenz Julienne , Florian Fainelli , Ray Jui , Scott Branden , Jonathan Derrick , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, linux-rockchip@lists.infradead.org, linux-rpi-kernel@lists.infradead.org, bcm-kernel-feedback-list@broadcom.com Subject: [PATCH v6 3/5] PCI: iproc: Convert to use the new ECAM constants Date: Sun, 29 Nov 2020 23:07:41 +0000 Message-Id: <20201129230743.3006978-4-kw@linux.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201129230743.3006978-1-kw@linux.com> References: <20201129230743.3006978-1-kw@linux.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Change interface of the function iproc_pcie_map_ep_cfg_reg() so that use of PCI_SLOT() and PCI_FUNC() macros and most of the local ECAM-specific constants can be dropped, and the new PCIE_ECAM_OFFSET() macro can be used instead. Use the ALIGN_DOWN() macro to ensure that PCI Express ECAM offset is always 32 bit aligned. Suggested-by: Bjorn Helgaas Signed-off-by: Krzysztof Wilczyński --- drivers/pci/controller/pcie-iproc.c | 31 ++++++++--------------------- 1 file changed, 8 insertions(+), 23 deletions(-) diff --git a/drivers/pci/controller/pcie-iproc.c b/drivers/pci/controller/pcie-iproc.c index 905e93808243..503662380ff8 100644 --- a/drivers/pci/controller/pcie-iproc.c +++ b/drivers/pci/controller/pcie-iproc.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -39,16 +40,8 @@ #define CFG_IND_ADDR_MASK 0x00001ffc -#define CFG_ADDR_BUS_NUM_SHIFT 20 -#define CFG_ADDR_BUS_NUM_MASK 0x0ff00000 -#define CFG_ADDR_DEV_NUM_SHIFT 15 -#define CFG_ADDR_DEV_NUM_MASK 0x000f8000 -#define CFG_ADDR_FUNC_NUM_SHIFT 12 -#define CFG_ADDR_FUNC_NUM_MASK 0x00007000 -#define CFG_ADDR_REG_NUM_SHIFT 2 #define CFG_ADDR_REG_NUM_MASK 0x00000ffc -#define CFG_ADDR_CFG_TYPE_SHIFT 0 -#define CFG_ADDR_CFG_TYPE_MASK 0x00000003 +#define CFG_ADDR_CFG_TYPE_1 1 #define SYS_RC_INTX_MASK 0xf @@ -459,19 +452,15 @@ static inline void iproc_pcie_apb_err_disable(struct pci_bus *bus, static void __iomem *iproc_pcie_map_ep_cfg_reg(struct iproc_pcie *pcie, unsigned int busno, - unsigned int slot, - unsigned int fn, + unsigned int devfn, int where) { u16 offset; u32 val; /* EP device access */ - val = (busno << CFG_ADDR_BUS_NUM_SHIFT) | - (slot << CFG_ADDR_DEV_NUM_SHIFT) | - (fn << CFG_ADDR_FUNC_NUM_SHIFT) | - (where & CFG_ADDR_REG_NUM_MASK) | - (1 & CFG_ADDR_CFG_TYPE_MASK); + val = ALIGN_DOWN(PCIE_ECAM_OFFSET(busno, devfn, where), 4) | + CFG_ADDR_CFG_TYPE_1; iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_ADDR, val); offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_DATA); @@ -574,8 +563,6 @@ static int iproc_pcie_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) { struct iproc_pcie *pcie = iproc_data(bus); - unsigned int slot = PCI_SLOT(devfn); - unsigned int fn = PCI_FUNC(devfn); unsigned int busno = bus->number; void __iomem *cfg_data_p; unsigned int data; @@ -590,7 +577,7 @@ static int iproc_pcie_config_read(struct pci_bus *bus, unsigned int devfn, return ret; } - cfg_data_p = iproc_pcie_map_ep_cfg_reg(pcie, busno, slot, fn, where); + cfg_data_p = iproc_pcie_map_ep_cfg_reg(pcie, busno, devfn, where); if (!cfg_data_p) return PCIBIOS_DEVICE_NOT_FOUND; @@ -631,13 +618,11 @@ static void __iomem *iproc_pcie_map_cfg_bus(struct iproc_pcie *pcie, int busno, unsigned int devfn, int where) { - unsigned slot = PCI_SLOT(devfn); - unsigned fn = PCI_FUNC(devfn); u16 offset; /* root complex access */ if (busno == 0) { - if (slot > 0 || fn > 0) + if (PCIE_ECAM_DEVFN(devfn) > 0) return NULL; iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_IND_ADDR, @@ -649,7 +634,7 @@ static void __iomem *iproc_pcie_map_cfg_bus(struct iproc_pcie *pcie, return (pcie->base + offset); } - return iproc_pcie_map_ep_cfg_reg(pcie, busno, slot, fn, where); + return iproc_pcie_map_ep_cfg_reg(pcie, busno, devfn, where); } static void __iomem *iproc_pcie_bus_map_cfg_bus(struct pci_bus *bus, -- 2.29.2