linux-pci.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Rob Herring <robh@kernel.org>
Cc: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>,
	bhelgaas@google.com, lorenzo.pieralisi@arm.com,
	linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	mgross@linux.intel.com, lakshmi.bai.raja.subramanian@intel.com
Subject: Re: [PATCH v3 2/2] PCI: keembay: Add support for Intel Keem Bay
Date: Wed, 9 Dec 2020 20:42:14 +0200	[thread overview]
Message-ID: <20201209184214.GV4077@smile.fi.intel.com> (raw)
In-Reply-To: <20201209181350.GB660537@robh.at.kernel.org>

On Wed, Dec 09, 2020 at 12:13:50PM -0600, Rob Herring wrote:
> On Wed, Dec 02, 2020 at 03:31:56PM +0800, Wan Ahmad Zainie wrote:

...

> > +static void keembay_pcie_ltssm_enable(struct keembay_pcie *pcie, bool enable)
> > +{
> > +	u32 val;
> > +
> > +	val = keembay_pcie_readl(pcie, PCIE_REGS_PCIE_APP_CNTRL);
> > +	if (enable)
> > +		val |= APP_LTSSM_ENABLE;
> > +	else
> > +		val &= ~APP_LTSSM_ENABLE;
> > +	keembay_pcie_writel(pcie, PCIE_REGS_PCIE_APP_CNTRL, val);
> 
> If this is the only bit in this register, do you really need RMW?

I think it's safer than do direct write and have something wrong on next
generations of hardware.

...

> > +static int keembay_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> > +				     enum pci_epc_irq_type type,
> > +				     u16 interrupt_num)
> > +{
> > +	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > +
> > +	switch (type) {
> > +	case PCI_EPC_IRQ_LEGACY:
> > +		/* Legacy interrupts are not supported in Keem Bay */
> > +		dev_err(pci->dev, "Legacy IRQ is not supported\n");
> > +		return -EINVAL;
> > +	case PCI_EPC_IRQ_MSI:
> > +		return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
> > +	case PCI_EPC_IRQ_MSIX:
> > +		return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
> > +	default:
> > +		dev_err(pci->dev, "Unknown IRQ type %d\n", type);
> > +		return -EINVAL;
> > +	}
> 
> Doesn't the lack of a 'return' give a warning?

Where? I don't see any lack of return.

> > +}

-- 
With Best Regards,
Andy Shevchenko



  reply	other threads:[~2020-12-09 18:43 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-02  7:31 [PATCH v3 0/2] PCI: keembay: Add support for Intel Keem Bay Wan Ahmad Zainie
2020-12-02  7:31 ` [PATCH v3 1/2] dt-bindings: PCI: Add Intel Keem Bay PCIe controller Wan Ahmad Zainie
2020-12-09 18:15   ` Rob Herring
2020-12-02  7:31 ` [PATCH v3 2/2] PCI: keembay: Add support for Intel Keem Bay Wan Ahmad Zainie
2020-12-09 18:13   ` Rob Herring
2020-12-09 18:42     ` Andy Shevchenko [this message]
2020-12-10 17:46       ` Rob Herring
2020-12-14 13:03         ` Wan Mohamad, Wan Ahmad Zainie
2020-12-14 15:00           ` Rob Herring
2020-12-14 15:34         ` Andy Shevchenko

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20201209184214.GV4077@smile.fi.intel.com \
    --to=andriy.shevchenko@linux.intel.com \
    --cc=bhelgaas@google.com \
    --cc=devicetree@vger.kernel.org \
    --cc=lakshmi.bai.raja.subramanian@intel.com \
    --cc=linux-pci@vger.kernel.org \
    --cc=lorenzo.pieralisi@arm.com \
    --cc=mgross@linux.intel.com \
    --cc=robh@kernel.org \
    --cc=wan.ahmad.zainie.wan.mohamad@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).