From: Jianjun Wang <jianjun.wang@mediatek.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
Rob Herring <robh+dt@kernel.org>, <maz@kernel.org>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Ryder Lee <ryder.lee@mediatek.com>
Cc: Philipp Zabel <p.zabel@pengutronix.de>,
Matthias Brugger <matthias.bgg@gmail.com>,
<linux-pci@vger.kernel.org>, <linux-mediatek@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
Sj Huang <sj.huang@mediatek.com>,
Jianjun Wang <jianjun.wang@mediatek.com>,
<youlin.pei@mediatek.com>, <chuanjia.liu@mediatek.com>,
<qizhong.cheng@mediatek.com>, <sin_jieyang@mediatek.com>,
<drinkcat@chromium.org>, <Rex-BC.Chen@mediatek.com>,
<anson.chuang@mediatek.com>
Subject: [v7,6/7] PCI: mediatek-gen3: Add system PM support
Date: Wed, 13 Jan 2021 19:40:00 +0800 [thread overview]
Message-ID: <20210113114001.5804-7-jianjun.wang@mediatek.com> (raw)
In-Reply-To: <20210113114001.5804-1-jianjun.wang@mediatek.com>
Add suspend_noirq and resume_noirq callback functions to implement
PM system suspend hooks for MediaTek Gen3 PCIe controller.
When system suspend, trigger the PCIe link to L2 state and pull down
the PERST# pin, gating the clocks of MAC layer and power off the
physical layer for the sake of power saving.
When system resum, the PCIe link should be re-established and the
related control register values should be restored.
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
---
drivers/pci/controller/pcie-mediatek-gen3.c | 78 +++++++++++++++++++++
1 file changed, 78 insertions(+)
diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
index 152820f28da1..ac6c43cea575 100644
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -49,6 +49,9 @@
#define PCIE_PE_RSTB BIT(3)
#define PCIE_LTSSM_STATUS_REG 0x150
+#define PCIE_LTSSM_STATE_MASK GENMASK(28, 24)
+#define PCIE_LTSSM_STATE(val) ((val & PCIE_LTSSM_STATE_MASK) >> 24)
+#define PCIE_LTSSM_STATE_L2_IDLE 0x14
#define PCIE_LINK_STATUS_REG 0x154
#define PCIE_PORT_LINKUP BIT(8)
@@ -76,6 +79,9 @@
#define PCIE_MSI_SET_ADDR_HI_BASE 0xc80
#define PCIE_MSI_SET_ADDR_HI_OFFSET 0x04
+#define PCIE_ICMD_PM_REG 0x198
+#define PCIE_TURN_OFF_LINK BIT(4)
+
#define PCIE_TRANS_TABLE_BASE_REG 0x800
#define PCIE_ATR_SRC_ADDR_MSB_OFFSET 0x4
#define PCIE_ATR_TRSL_ADDR_LSB_OFFSET 0x8
@@ -869,6 +875,77 @@ static int mtk_pcie_remove(struct platform_device *pdev)
return 0;
}
+static int __maybe_unused mtk_pcie_turn_off_link(struct mtk_pcie_port *port)
+{
+ u32 val;
+
+ val = readl_relaxed(port->base + PCIE_ICMD_PM_REG);
+ val |= PCIE_TURN_OFF_LINK;
+ writel_relaxed(val, port->base + PCIE_ICMD_PM_REG);
+
+ /* Check the link is L2 */
+ return readl_poll_timeout(port->base + PCIE_LTSSM_STATUS_REG, val,
+ (PCIE_LTSSM_STATE(val) ==
+ PCIE_LTSSM_STATE_L2_IDLE), 20,
+ 50 * USEC_PER_MSEC);
+}
+
+static int __maybe_unused mtk_pcie_suspend_noirq(struct device *dev)
+{
+ struct mtk_pcie_port *port = dev_get_drvdata(dev);
+ int err;
+ u32 val;
+
+ /* Trigger link to L2 state */
+ err = mtk_pcie_turn_off_link(port);
+ if (err) {
+ dev_err(port->dev, "can not enter L2 state\n");
+ return err;
+ }
+
+ /* Pull down the PERST# pin */
+ val = readl_relaxed(port->base + PCIE_RST_CTRL_REG);
+ val |= PCIE_PE_RSTB;
+ writel_relaxed(val, port->base + PCIE_RST_CTRL_REG);
+
+ dev_dbg(port->dev, "enter L2 state success");
+
+ clk_bulk_disable_unprepare(port->num_clks, port->clks);
+
+ phy_power_off(port->phy);
+
+ return 0;
+}
+
+static int __maybe_unused mtk_pcie_resume_noirq(struct device *dev)
+{
+ struct mtk_pcie_port *port = dev_get_drvdata(dev);
+ int err;
+
+ phy_power_on(port->phy);
+
+ err = clk_bulk_prepare_enable(port->num_clks, port->clks);
+ if (err) {
+ dev_dbg(dev, "failed to enable PCIe clocks\n");
+ return err;
+ }
+
+ err = mtk_pcie_startup_port(port);
+ if (err) {
+ dev_err(port->dev, "resume failed\n");
+ return err;
+ }
+
+ dev_dbg(port->dev, "resume done\n");
+
+ return 0;
+}
+
+static const struct dev_pm_ops mtk_pcie_pm_ops = {
+ SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_pcie_suspend_noirq,
+ mtk_pcie_resume_noirq)
+};
+
static const struct of_device_id mtk_pcie_of_match[] = {
{ .compatible = "mediatek,mt8192-pcie" },
{},
@@ -880,6 +957,7 @@ static struct platform_driver mtk_pcie_driver = {
.driver = {
.name = "mtk-pcie",
.of_match_table = mtk_pcie_of_match,
+ .pm = &mtk_pcie_pm_ops,
},
};
--
2.25.1
next prev parent reply other threads:[~2021-01-13 11:42 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-13 11:39 [v7,0/7] PCI: mediatek: Add new generation controller support Jianjun Wang
2021-01-13 11:39 ` [v7,1/7] dt-bindings: PCI: mediatek-gen3: Add YAML schema Jianjun Wang
2021-01-25 20:22 ` Rob Herring
2021-01-26 12:01 ` Jianjun Wang
2021-01-13 11:39 ` [v7,2/7] PCI: Export pci_pio_to_address() for module use Jianjun Wang
2021-01-13 11:39 ` [v7,3/7] PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192 Jianjun Wang
2021-01-25 19:54 ` Rob Herring
2021-01-26 11:42 ` Jianjun Wang
2021-01-13 11:39 ` [v7,4/7] PCI: mediatek-gen3: Add INTx support Jianjun Wang
2021-01-26 12:25 ` Marc Zyngier
2021-01-27 13:09 ` Jianjun Wang
2021-01-13 11:39 ` [v7,5/7] PCI: mediatek-gen3: Add MSI support Jianjun Wang
2021-01-26 13:57 ` Marc Zyngier
2021-01-27 12:31 ` Jianjun Wang
2021-01-27 13:05 ` Marc Zyngier
2021-01-27 13:17 ` Jianjun Wang
2021-01-13 11:40 ` Jianjun Wang [this message]
2021-01-13 11:40 ` [v7,7/7] MAINTAINERS: Add Jianjun Wang as MediaTek PCI co-maintainer Jianjun Wang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210113114001.5804-7-jianjun.wang@mediatek.com \
--to=jianjun.wang@mediatek.com \
--cc=Rex-BC.Chen@mediatek.com \
--cc=anson.chuang@mediatek.com \
--cc=bhelgaas@google.com \
--cc=chuanjia.liu@mediatek.com \
--cc=devicetree@vger.kernel.org \
--cc=drinkcat@chromium.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=linux-pci@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=matthias.bgg@gmail.com \
--cc=maz@kernel.org \
--cc=p.zabel@pengutronix.de \
--cc=qizhong.cheng@mediatek.com \
--cc=robh+dt@kernel.org \
--cc=ryder.lee@mediatek.com \
--cc=sin_jieyang@mediatek.com \
--cc=sj.huang@mediatek.com \
--cc=youlin.pei@mediatek.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).