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From: Tony Lindgren <tony@atomide.com>
To: linux-omap@vger.kernel.org
Cc: "Benoît Cousson" <bcousson@baylibre.com>,
	devicetree@vger.kernel.org, "Bjorn Helgaas" <bhelgaas@google.com>,
	"Kishon Vijay Abraham I" <kishon@ti.com>,
	"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
	"Vignesh Raghavendra" <vigneshr@ti.com>,
	linux-pci@vger.kernel.org
Subject: [PATCH 07/15] ARM: dts: Configure interconnect target module for dra7 sata
Date: Tue, 26 Jan 2021 14:39:56 +0200	[thread overview]
Message-ID: <20210126124004.52550-8-tony@atomide.com> (raw)
In-Reply-To: <20210126124004.52550-1-tony@atomide.com>

We can now probe devices with device tree only configuration using
ti-sysc interconnect target module driver. Let's configure the
module, but keep the legacy "ti,hwmods" peroperty to avoid new boot
time warnings. The legacy property will be removed in later patches
together with the legacy platform data.

Note that the old sysc register offset is wrong, the real offset is at
0x1100 as listed in TRM for SATA_SYSCONFIG register. Looks like we've been
happily using sata on the bootloader configured sysconfig register and
nobody noticed. Also the old register range for SATAMAC_wrapper registers
is wrong at 7 while it should be 8. But that too seems harmless.

There is also an L3 parent interconnect range that we don't seem to be
using. That can be added as needed later on.

Signed-off-by: Tony Lindgren <tony@atomide.com>
---
 arch/arm/boot/dts/dra7-l4.dtsi | 29 ++++++++++++++++++++++++++---
 arch/arm/boot/dts/dra7.dtsi    | 12 ------------
 2 files changed, 26 insertions(+), 15 deletions(-)

diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi
--- a/arch/arm/boot/dts/dra7-l4.dtsi
+++ b/arch/arm/boot/dts/dra7-l4.dtsi
@@ -572,11 +572,34 @@ target-module@8000 {			/* 0x4a108000, ap 29 1e.0 */
 		};
 
 		target-module@40000 {			/* 0x4a140000, ap 31 06.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
+			compatible = "ti,sysc-omap4", "ti,sysc";
+			ti,hwmods = "sata";
+			reg = <0x400fc 4>,
+			      <0x41100 4>;
+			reg-names = "rev", "sysc";
+			ti,sysc-midle = <SYSC_IDLE_FORCE>,
+					<SYSC_IDLE_NO>,
+					<SYSC_IDLE_SMART>;
+			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+					<SYSC_IDLE_NO>,
+					<SYSC_IDLE_SMART>,
+					<SYSC_IDLE_SMART_WKUP>;
+			power-domains = <&prm_l3init>;
+			clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 0>;
+			clock-names = "fck";
 			#size-cells = <1>;
+			#address-cells = <1>;
 			ranges = <0x0 0x40000 0x10000>;
+
+			sata: sata@0 {
+				compatible = "snps,dwc-ahci";
+				reg = <0 0x1100>, <0x1100 0x8>;
+				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+				phys = <&sata_phy>;
+				phy-names = "sata-phy";
+				clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>;
+				ports-implemented = <0x1>;
+			};
 		};
 
 		target-module@51000 {			/* 0x4a151000, ap 33 50.0 */
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -785,18 +785,6 @@ qspi: spi@0 {
 			};
 		};
 
-		/* OCP2SCP3 */
-		sata: sata@4a141100 {
-			compatible = "snps,dwc-ahci";
-			reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
-			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
-			phys = <&sata_phy>;
-			phy-names = "sata-phy";
-			clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>;
-			ti,hwmods = "sata";
-			ports-implemented = <0x1>;
-		};
-
 		/* OCP2SCP1 */
 		/* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
 
-- 
2.30.0

  parent reply	other threads:[~2021-01-26 12:43 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-26 12:39 [PATCHv2 00/15] Update dra7 devicetree files to probe with genpd Tony Lindgren
2021-01-26 12:39 ` [PATCH 01/15] PCI: pci-dra7xx: Prepare for deferred probe with module_platform_driver Tony Lindgren
2021-01-28  8:54   ` Tony Lindgren
2021-01-26 12:39 ` [PATCH 02/15] ARM: dts: Update pcie ranges for dra7 Tony Lindgren
2021-01-26 12:39 ` [PATCH 03/15] ARM: dts: Configure interconnect target module for dra7 pcie Tony Lindgren
2021-01-26 12:39 ` [PATCH 04/15] ARM: dts: Properly configure dra7 edma sysconfig registers Tony Lindgren
2021-01-26 12:39 ` [PATCH 05/15] ARM: dts: Move dra7 l3 noc to a separate node Tony Lindgren
2021-01-26 12:39 ` [PATCH 06/15] ARM: dts: Configure interconnect target module for dra7 qspi Tony Lindgren
2021-01-26 12:39 ` Tony Lindgren [this message]
2021-01-26 12:39 ` [PATCH 08/15] ARM: dts: Configure interconnect target module for dra7 mpu Tony Lindgren
2021-03-08 11:53   ` Tony Lindgren
2021-01-26 12:39 ` [PATCH 09/15] ARM: dts: Configure interconnect target module for dra7 dmm Tony Lindgren
2021-03-08 12:51   ` Tony Lindgren
2021-01-26 12:39 ` [PATCH 10/15] ARM: dts: Configure simple-pm-bus for dra7 l4_wkup Tony Lindgren
2021-01-26 12:40 ` [PATCH 11/15] ARM: dts: Configure simple-pm-bus for dra7 l4_per1 Tony Lindgren
2021-01-26 12:40 ` [PATCH 12/15] ARM: dts: Configure simple-pm-bus for dra7 l4_per2 Tony Lindgren
2021-01-26 12:40 ` [PATCH 13/15] ARM: dts: Configure simple-pm-bus for dra7 l4_per3 Tony Lindgren
2021-01-26 12:40 ` [PATCH 14/15] ARM: dts: Configure simple-pm-bus for dra7 l4_cfg Tony Lindgren
2021-01-26 12:40 ` [PATCH 15/15] ARM: dts: Configure simple-pm-bus for dra7 l3 Tony Lindgren
2021-03-08 11:20 ` [PATCHv2 00/15] Update dra7 devicetree files to probe with genpd Kishon Vijay Abraham I

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