From: Bjorn Helgaas <firstname.lastname@example.org> To: "Marek Behún" <email@example.com> Cc: firstname.lastname@example.org, Rötti <email@example.com>, "Pali Rohár" <firstname.lastname@example.org>, email@example.com, "Zachary Zhang" <firstname.lastname@example.org> Subject: Re: [PATCH] PCI: Add Max Payload Size quirk for ASMedia ASM1062 SATA controller Date: Wed, 17 Mar 2021 17:45:49 -0500 [thread overview] Message-ID: <20210317224549.GA93134@bjorn-Precision-5520> (raw) In-Reply-To: <email@example.com> [+cc Zachary, author of 8a3ebd8de328] Thanks for the report and the patch, Marek! On Wed, Mar 17, 2021 at 12:59:24PM +0100, Marek Behún wrote: > The ASMedia ASM1062 SATA controller causes an External Abort on > controllers which support Max Payload Size >= 512. It happens with > Aardvark PCIe controller (tested on Turris MOX) and also with DesignWare > controller (armada8k, tested on CN9130-CRB): > > ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300) > ata1.00: ATA-9: WDC WD40EFRX-68WT0N0, 80.00A80, max UDMA/133 > ata1.00: 7814037168 sectors, multi 0: LBA48 NCQ (depth 32), AA > ERROR: Unhandled External Abort received on 0x80000000 at EL3! > ERROR: exception reason=1 syndrome=0x92000210 > PANIC at PC : 0x00000000040273bc > > Limiting Max Payload Size to 256 bytes solves this problem. > > On Turris MOX this problem first appeared when the pci-aardvark > controller started using the pci-emul-bridge API, in commit 8a3ebd8de328 > ("PCI: aardvark: Implement emulated root PCI bridge config space"). Any ideas about why 8a3ebd8de328 made a difference? Could there be a defect in 8a3ebd8de328? Or maybe before 8a3ebd8de328 we didn't actually read or update MPS settings in the hardware? > On armada8k this was always a problem because it has HW root bridge. Can you please open a report at bugzilla.kernel.org and attach the complete "sudo lspci -vv" output for both systems? I think it's OK to collect these with the patch applied; we should still be able to see the information we use to compute the MPS values. But please include the CONFIG_PCIE_BUS_* settings and any "pcie_bus_*" kernel command line arguments. This quirk suggests that there's a hardware defect in the ASMedia ASM1062. But if that's really the case, we should see reports on lots of platforms, and I'm only aware of these two. You do mention that it was always a problem on armada8k; if you know of other reports of that, please include URLs in the bugzilla. If the problem only occurs on these platforms, my first guess would be a hardware defect in these platforms or a software defect in the PCIe controller driver. It wouldn't surprise me if we have a generic PCI core defect in how we set MPS, either. > Signed-off-by: Marek Behún <firstname.lastname@example.org> > Reported-by: Rötti <email@example.com> > Cc: Pali Rohár <firstname.lastname@example.org> > Cc: email@example.com > --- > drivers/pci/quirks.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c > index 653660e3ba9e..a561136efb08 100644 > --- a/drivers/pci/quirks.c > +++ b/drivers/pci/quirks.c > @@ -3251,6 +3251,11 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, > PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256); > DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, > PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); > +/* > + * For some reason DECLARE_PCI_FIXUP_HEADER does not work with pci-aardvark > + * controller. We have to use DECLARE_PCI_FIXUP_EARLY. > + */ This is curious, too. If we need the quirk, I'd like to run this down to figure out why we need an EARLY instead of HEADER quirk. Differences like that suggest a bug elsewhere, or at least an unnecessary difference between PCIe controller drivers. > +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ASMEDIA, 0x0612, fixup_mpss_256); > > /* > * Intel 5000 and 5100 Memory controllers have an erratum with read completion > -- > 2.26.2 >
next prev parent reply other threads:[~2021-03-17 22:46 UTC|newest] Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-03-17 11:59 Marek Behún 2021-03-17 18:46 ` Pali Rohár 2021-03-17 22:45 ` Bjorn Helgaas [this message] 2021-03-17 22:55 ` Pali Rohár 2021-03-17 23:03 ` Bjorn Helgaas 2021-03-19 19:02 ` Pali Rohár 2021-03-21 15:09 ` Rötti 2021-05-30 10:21 ` Pali Rohár 2021-08-26 11:00 ` Rötti 2021-03-17 23:09 ` Marek Behún 2021-04-16 13:54 ` Marek Behún 2021-04-25 15:29 ` Pali Rohár 2021-05-11 16:16 ` Marek Behún 2021-05-28 0:12 ` Pali Rohár 2021-06-01 17:09 ` Bjorn Helgaas 2021-06-01 21:15 ` Bjorn Helgaas 2021-06-01 11:36 ` Krzysztof Wilczyński
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