Re: [PATCH] PCI: Add Max Payload Size quirk for ASMedia ASM1062 SATA controller

["Marek Behún" <kabel@kernel.org>]

On Wed, 17 Mar 2021 17:45:49 -0500
Bjorn Helgaas <helgaas@kernel.org> wrote:

> [+cc Zachary, author of 8a3ebd8de328]
> 
> Thanks for the report and the patch, Marek!
> 
> On Wed, Mar 17, 2021 at 12:59:24PM +0100, Marek Behún wrote:
> > The ASMedia ASM1062 SATA controller causes an External Abort on
> > controllers which support Max Payload Size >= 512. It happens with
> > Aardvark PCIe controller (tested on Turris MOX) and also with DesignWare
> > controller (armada8k, tested on CN9130-CRB):
> > 
> >   ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
> >   ata1.00: ATA-9: WDC WD40EFRX-68WT0N0, 80.00A80, max UDMA/133
> >   ata1.00: 7814037168 sectors, multi 0: LBA48 NCQ (depth 32), AA
> >   ERROR:   Unhandled External Abort received on 0x80000000 at EL3!
> >   ERROR:    exception reason=1 syndrome=0x92000210
> >   PANIC at PC : 0x00000000040273bc
> > 
> > Limiting Max Payload Size to 256 bytes solves this problem.
> > 
> > On Turris MOX this problem first appeared when the pci-aardvark
> > controller started using the pci-emul-bridge API, in commit 8a3ebd8de328
> > ("PCI: aardvark: Implement emulated root PCI bridge config space").  
> 
> Any ideas about why 8a3ebd8de328 made a difference?  Could there be a
> defect in 8a3ebd8de328?  Or maybe before 8a3ebd8de328 we didn't
> actually read or update MPS settings in the hardware?

Before 8a3ebd8de328 the PCIe subsystem could not detect that the MPS is
512 bytes, because the emulated bridge did not exists. So it did not try
to change MPS for the SATA controller, or changed it to minimum of 128
bytes. Once pci-emul-bridge was added, the PCIe subsystem had access to
the information that the aardvark controller supports 512 bytes, so it
tried to leverage it, since the SATA controller says it can handle 512
bytes MPS. But apparently it cannot.

> > On armada8k this was always a problem because it has HW root bridge.  
> 
> Can you please open a report at bugzilla.kernel.org and attach the
> complete "sudo lspci -vv" output for both systems?  I think it's OK to
> collect these with the patch applied; we should still be able to see
> the information we use to compute the MPS values.  But please include
> the CONFIG_PCIE_BUS_* settings and any "pcie_bus_*" kernel command
> line arguments.
> 
> This quirk suggests that there's a hardware defect in the ASMedia
> ASM1062.  But if that's really the case, we should see reports on lots
> of platforms, and I'm only aware of these two.  You do mention that it
> was always a problem on armada8k; if you know of other reports of
> that, please include URLs in the bugzilla.

I think that most people use this adapter on x86 platforms. Maybe x86
PCIe controllers do not support 512 bytes MPS (at least my notebook
nor work computer don't). So this issue would be only detected by
someone who used this controller on a controller which supports 512+
bytes MPS. armada8k is mainly used for network devices, so PCIe
there is probably mostly used for wifi cards, and for SATA armada8k has
native controller, and also nVME. The most probable answer is that
noone used this controller on armada8k nor aardvark...

> If the problem only occurs on these platforms, my first guess would be
> a hardware defect in these platforms or a software defect in the PCIe
> controller driver.  It wouldn't surprise me if we have a generic PCI
> core defect in how we set MPS, either.

If someone has this card and a x86 or other PCIe controller capable of
512 byte MPS, maybe they could check.

But aramda8k PCIe controller (which is a DesignWare IP) is completely
different from aardvark (although they both are on Armada SOCs). I
think it is more probable that the problem is in the ASMedia SATA
controller, this controller has also other issues (firmware sometimes
crashing, for example).

> > Signed-off-by: Marek Behún <kabel@kernel.org>
> > Reported-by: Rötti <espressobinboardarmbiantempmailaddress@posteo.de>
> > Cc: Pali Rohár <pali@kernel.org>
> > Cc: stable@vger.kernel.org
> > ---
> >  drivers/pci/quirks.c | 5 +++++
> >  1 file changed, 5 insertions(+)
> > 
> > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> > index 653660e3ba9e..a561136efb08 100644
> > --- a/drivers/pci/quirks.c
> > +++ b/drivers/pci/quirks.c
> > @@ -3251,6 +3251,11 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
> >  			 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
> >  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
> >  			 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
> > +/*
> > + * For some reason DECLARE_PCI_FIXUP_HEADER does not work with pci-aardvark
> > + * controller. We have to use DECLARE_PCI_FIXUP_EARLY.
> > + */  
> 
> This is curious, too.  If we need the quirk, I'd like to run this down
> to figure out why we need an EARLY instead of HEADER quirk.
> Differences like that suggest a bug elsewhere, or at least an
> unnecessary difference between PCIe controller drivers.

Now that I look at this, the comment is wrong. What I meant to say is
that when I used HEADER quirk, the PCIe subsystem did change the MPS to
512 bytes, so clearly the HAEDER quirk only comes after changing of MPS.

I think that the other quirks using the fixup_mpss_256 callback should
also use EARLY instead of HEADER. Maybe something changed in PCI API
sometime and noone noticed that these quirks stopped working?

Marek

> > +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ASMEDIA, 0x0612, fixup_mpss_256);
> >  
> >  /*
> >   * Intel 5000 and 5100 Memory controllers have an erratum with read completion
> > -- 
> > 2.26.2
> >