From: Chunyan Zhang <zhang.lyra@gmail.com>
To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Rob Herring <robh+dt@kernel.org>
Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
Hongtao Wu <wuht06@gmail.com>,
Baolin Wang <baolin.wang7@gmail.com>,
linux-kernel@vger.kernel.org, Orson Zhai <orsonzhai@gmail.com>,
Chunyan Zhang <zhang.lyra@gmail.com>,
Chunyan Zhang <chunyan.zhang@unisoc.com>
Subject: [RESEND PATCH V6 1/2] dt-bindings: PCI: sprd: Document Unisoc PCIe RC host controller
Date: Mon, 22 Mar 2021 17:18:30 +0800 [thread overview]
Message-ID: <20210322091831.662279-2-zhang.lyra@gmail.com> (raw)
In-Reply-To: <20210322091831.662279-1-zhang.lyra@gmail.com>
From: Hongtao Wu <billows.wu@unisoc.com>
This series adds PCIe bindings for Unisoc SoCs.
This controller is based on DesignWare PCIe IP.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Hongtao Wu <billows.wu@unisoc.com>
Signed-off-by: Chunyan Zhang <zhang.lyra@gmail.com>
---
.../devicetree/bindings/pci/sprd-pcie.yaml | 93 +++++++++++++++++++
1 file changed, 93 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/sprd-pcie.yaml
diff --git a/Documentation/devicetree/bindings/pci/sprd-pcie.yaml b/Documentation/devicetree/bindings/pci/sprd-pcie.yaml
new file mode 100644
index 000000000000..ede06a80d24f
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/sprd-pcie.yaml
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/sprd-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SoC PCIe Host Controller Device Tree Bindings
+
+maintainers:
+ - Hongtao Wu <billows.wu@unisoc.com>
+
+allOf:
+ - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: sprd,ums9520-pcie
+
+ reg:
+ minItems: 2
+ items:
+ - description: Controller control and status registers.
+ - description: PCIe configuration registers.
+
+ reg-names:
+ items:
+ - const: dbi
+ - const: config
+
+ ranges:
+ maxItems: 2
+
+ num-lanes:
+ maximum: 1
+ description: Number of lanes to use for this port.
+
+ interrupts:
+ minItems: 1
+ description: Builtin MSI controller and PCIe host controller.
+
+ interrupt-names:
+ items:
+ - const: msi
+
+ sprd,regmap-aon:
+ $ref: '/schemas/types.yaml#/definitions/phandle'
+ description:
+ Phandle to the AON system controller node (to access the
+ AON_ACCESS_PCIE_EN register on ums9520).
+ sprd,regmap-pmu:
+ $ref: '/schemas/types.yaml#/definitions/phandle'
+ description:
+ Phandle to the PMU system controller node (to access the PERST_N_ASSERT
+ register on ums9520).
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - num-lanes
+ - ranges
+ - interrupts
+ - interrupt-names
+
+additionalProperties: true
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ ipa {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie0: pcie@2b100000 {
+ compatible = "sprd,ums9520-pcie";
+ reg = <0x0 0x2b100000 0x0 0x2000>,
+ <0x2 0x00000000 0x0 0x2000>;
+ reg-names = "dbi", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x01000000 0x0 0x00000000 0x2 0x00002000 0x0 0x00010000>,
+ <0x03000000 0x0 0x10000000 0x2 0x10000000 0x1 0xefffffff>;
+ num-lanes = <1>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+
+ sprd,regmap-aon = <&aon_regs>;
+ sprd,regmap-pmu = <&pmu_regs>;
+ };
+ };
--
2.25.1
next prev parent reply other threads:[~2021-03-22 9:21 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-22 9:18 [RESEND PATCH V6 0/2] PCI: Add new Unisoc PCIe driver Chunyan Zhang
2021-03-22 9:18 ` Chunyan Zhang [this message]
2021-03-22 9:18 ` [RESEND PATCH V6 2/2] PCI: sprd: Add support for Unisoc SoCs' PCIe controller Chunyan Zhang
2021-03-23 20:30 ` Bjorn Helgaas
2021-03-25 6:14 ` Chunyan Zhang
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