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* [PATCH v2] PCI: controller: convert to devm_platform_ioremap_resource_byname()
@ 2020-06-02 17:16 Dejin Zheng
  2020-07-07 11:31 ` Lorenzo Pieralisi
  2021-03-27 18:02 ` dann frazier
  0 siblings, 2 replies; 5+ messages in thread
From: Dejin Zheng @ 2020-06-02 17:16 UTC (permalink / raw)
  To: tjoseph, lorenzo.pieralisi, robh, bhelgaas, thierry.reding, toan,
	ley.foon.tan, shawn.lin, linux-pci, linux-kernel
  Cc: Dejin Zheng

Use devm_platform_ioremap_resource_byname() to simplify codes.
it contains platform_get_resource_byname() and devm_ioremap_resource().

Signed-off-by: Dejin Zheng <zhengdejin5@gmail.com>
---
v1 -> v2:
	- Discard changes to the file drivers/pci/controller/pcie-xilinx-nwl.c
	  Due to my mistakes, my patch will modify pcie-xilinx-nwl.c,
	  but it still need to use the res variable, but
	  devm_platform_ioremap_resource_byname() funtion can't assign a
	  value to the variable res. kbuild test robot report it. Thanks
	  very much for kbuild test robot <lkp@intel.com>.

 drivers/pci/controller/cadence/pcie-cadence-ep.c   | 3 +--
 drivers/pci/controller/cadence/pcie-cadence-host.c | 3 +--
 drivers/pci/controller/pci-tegra.c                 | 8 +++-----
 drivers/pci/controller/pci-xgene.c                 | 3 +--
 drivers/pci/controller/pcie-altera-msi.c           | 3 +--
 drivers/pci/controller/pcie-altera.c               | 9 +++------
 drivers/pci/controller/pcie-mediatek.c             | 4 +---
 drivers/pci/controller/pcie-rockchip.c             | 5 ++---
 8 files changed, 13 insertions(+), 25 deletions(-)

diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c
index 1c15c8352125..74ffa03fde5f 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-ep.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c
@@ -408,8 +408,7 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)
 
 	pcie->is_rc = false;
 
-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
-	pcie->reg_base = devm_ioremap_resource(dev, res);
+	pcie->reg_base = devm_platform_ioremap_resource_byname(pdev, "reg");
 	if (IS_ERR(pcie->reg_base)) {
 		dev_err(dev, "missing \"reg\"\n");
 		return PTR_ERR(pcie->reg_base);
diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
index 8c2543f28ba0..dcc460a54875 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-host.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
@@ -225,8 +225,7 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
 	rc->device_id = 0xffff;
 	of_property_read_u32(np, "device-id", &rc->device_id);
 
-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
-	pcie->reg_base = devm_ioremap_resource(dev, res);
+	pcie->reg_base = devm_platform_ioremap_resource_byname(pdev, "reg");
 	if (IS_ERR(pcie->reg_base)) {
 		dev_err(dev, "missing \"reg\"\n");
 		return PTR_ERR(pcie->reg_base);
diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
index e3e917243e10..3e608383df66 100644
--- a/drivers/pci/controller/pci-tegra.c
+++ b/drivers/pci/controller/pci-tegra.c
@@ -1462,7 +1462,7 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
 {
 	struct device *dev = pcie->dev;
 	struct platform_device *pdev = to_platform_device(dev);
-	struct resource *pads, *afi, *res;
+	struct resource *res;
 	const struct tegra_pcie_soc *soc = pcie->soc;
 	int err;
 
@@ -1486,15 +1486,13 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
 		}
 	}
 
-	pads = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pads");
-	pcie->pads = devm_ioremap_resource(dev, pads);
+	pcie->pads = devm_platform_ioremap_resource_byname(pdev, "pads");
 	if (IS_ERR(pcie->pads)) {
 		err = PTR_ERR(pcie->pads);
 		goto phys_put;
 	}
 
-	afi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "afi");
-	pcie->afi = devm_ioremap_resource(dev, afi);
+	pcie->afi = devm_platform_ioremap_resource_byname(pdev, "afi");
 	if (IS_ERR(pcie->afi)) {
 		err = PTR_ERR(pcie->afi);
 		goto phys_put;
diff --git a/drivers/pci/controller/pci-xgene.c b/drivers/pci/controller/pci-xgene.c
index d1efa8ffbae1..1431a18eb02c 100644
--- a/drivers/pci/controller/pci-xgene.c
+++ b/drivers/pci/controller/pci-xgene.c
@@ -355,8 +355,7 @@ static int xgene_pcie_map_reg(struct xgene_pcie_port *port,
 	if (IS_ERR(port->csr_base))
 		return PTR_ERR(port->csr_base);
 
-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
-	port->cfg_base = devm_ioremap_resource(dev, res);
+	port->cfg_base = devm_platform_ioremap_resource_byname(pdev, "cfg");
 	if (IS_ERR(port->cfg_base))
 		return PTR_ERR(port->cfg_base);
 	port->cfg_addr = res->start;
diff --git a/drivers/pci/controller/pcie-altera-msi.c b/drivers/pci/controller/pcie-altera-msi.c
index 16d938920ca5..613e19af71bd 100644
--- a/drivers/pci/controller/pcie-altera-msi.c
+++ b/drivers/pci/controller/pcie-altera-msi.c
@@ -228,8 +228,7 @@ static int altera_msi_probe(struct platform_device *pdev)
 	mutex_init(&msi->lock);
 	msi->pdev = pdev;
 
-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csr");
-	msi->csr_base = devm_ioremap_resource(&pdev->dev, res);
+	msi->csr_base = devm_platform_ioremap_resource_byname(pdev, "csr");
 	if (IS_ERR(msi->csr_base)) {
 		dev_err(&pdev->dev, "failed to map csr memory\n");
 		return PTR_ERR(msi->csr_base);
diff --git a/drivers/pci/controller/pcie-altera.c b/drivers/pci/controller/pcie-altera.c
index 24cb1c331058..7200e40ffa26 100644
--- a/drivers/pci/controller/pcie-altera.c
+++ b/drivers/pci/controller/pcie-altera.c
@@ -696,17 +696,14 @@ static int altera_pcie_parse_dt(struct altera_pcie *pcie)
 {
 	struct device *dev = &pcie->pdev->dev;
 	struct platform_device *pdev = pcie->pdev;
-	struct resource *cra;
-	struct resource *hip;
 
-	cra = platform_get_resource_byname(pdev, IORESOURCE_MEM, "Cra");
-	pcie->cra_base = devm_ioremap_resource(dev, cra);
+	pcie->cra_base = devm_platform_ioremap_resource_byname(pdev, "Cra");
 	if (IS_ERR(pcie->cra_base))
 		return PTR_ERR(pcie->cra_base);
 
 	if (pcie->pcie_data->version == ALTERA_PCIE_V2) {
-		hip = platform_get_resource_byname(pdev, IORESOURCE_MEM, "Hip");
-		pcie->hip_base = devm_ioremap_resource(&pdev->dev, hip);
+		pcie->hip_base =
+			devm_platform_ioremap_resource_byname(pdev, "Hip");
 		if (IS_ERR(pcie->hip_base))
 			return PTR_ERR(pcie->hip_base);
 	}
diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
index ebfa7d5a4e2d..d8e38276dbe3 100644
--- a/drivers/pci/controller/pcie-mediatek.c
+++ b/drivers/pci/controller/pcie-mediatek.c
@@ -905,7 +905,6 @@ static int mtk_pcie_parse_port(struct mtk_pcie *pcie,
 			       int slot)
 {
 	struct mtk_pcie_port *port;
-	struct resource *regs;
 	struct device *dev = pcie->dev;
 	struct platform_device *pdev = to_platform_device(dev);
 	char name[10];
@@ -916,8 +915,7 @@ static int mtk_pcie_parse_port(struct mtk_pcie *pcie,
 		return -ENOMEM;
 
 	snprintf(name, sizeof(name), "port%d", slot);
-	regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
-	port->base = devm_ioremap_resource(dev, regs);
+	port->base = devm_platform_ioremap_resource_byname(pdev, name);
 	if (IS_ERR(port->base)) {
 		dev_err(dev, "failed to map port%d base\n", slot);
 		return PTR_ERR(port->base);
diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c
index c53d1322a3d6..904dec0d3a88 100644
--- a/drivers/pci/controller/pcie-rockchip.c
+++ b/drivers/pci/controller/pcie-rockchip.c
@@ -45,9 +45,8 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
 			return -EINVAL;
 	}
 
-	regs = platform_get_resource_byname(pdev, IORESOURCE_MEM,
-					    "apb-base");
-	rockchip->apb_base = devm_ioremap_resource(dev, regs);
+	rockchip->apb_base =
+		devm_platform_ioremap_resource_byname(pdev, "apb-base");
 	if (IS_ERR(rockchip->apb_base))
 		return PTR_ERR(rockchip->apb_base);
 
-- 
2.25.0


^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH v2] PCI: controller: convert to devm_platform_ioremap_resource_byname()
  2020-06-02 17:16 [PATCH v2] PCI: controller: convert to devm_platform_ioremap_resource_byname() Dejin Zheng
@ 2020-07-07 11:31 ` Lorenzo Pieralisi
  2020-07-07 11:40   ` Lorenzo Pieralisi
  2021-03-27 18:02 ` dann frazier
  1 sibling, 1 reply; 5+ messages in thread
From: Lorenzo Pieralisi @ 2020-07-07 11:31 UTC (permalink / raw)
  To: Dejin Zheng
  Cc: tjoseph, robh, bhelgaas, thierry.reding, toan, ley.foon.tan,
	shawn.lin, linux-pci, linux-kernel

On Wed, Jun 03, 2020 at 01:16:01AM +0800, Dejin Zheng wrote:
> Use devm_platform_ioremap_resource_byname() to simplify codes.
> it contains platform_get_resource_byname() and devm_ioremap_resource().
> 
> Signed-off-by: Dejin Zheng <zhengdejin5@gmail.com>
> ---
> v1 -> v2:
> 	- Discard changes to the file drivers/pci/controller/pcie-xilinx-nwl.c
> 	  Due to my mistakes, my patch will modify pcie-xilinx-nwl.c,
> 	  but it still need to use the res variable, but
> 	  devm_platform_ioremap_resource_byname() funtion can't assign a
> 	  value to the variable res. kbuild test robot report it. Thanks
> 	  very much for kbuild test robot <lkp@intel.com>.
> 
>  drivers/pci/controller/cadence/pcie-cadence-ep.c   | 3 +--
>  drivers/pci/controller/cadence/pcie-cadence-host.c | 3 +--
>  drivers/pci/controller/pci-tegra.c                 | 8 +++-----
>  drivers/pci/controller/pci-xgene.c                 | 3 +--
>  drivers/pci/controller/pcie-altera-msi.c           | 3 +--
>  drivers/pci/controller/pcie-altera.c               | 9 +++------
>  drivers/pci/controller/pcie-mediatek.c             | 4 +---
>  drivers/pci/controller/pcie-rockchip.c             | 5 ++---
>  8 files changed, 13 insertions(+), 25 deletions(-)

Applied to pci/dwc with Rob and Gustavo's tags (next time please
carry them over and send v2 in-reply-to v1 so that I can follow
it), thanks.

Lorenzo

> diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c
> index 1c15c8352125..74ffa03fde5f 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c
> +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c
> @@ -408,8 +408,7 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)
>  
>  	pcie->is_rc = false;
>  
> -	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
> -	pcie->reg_base = devm_ioremap_resource(dev, res);
> +	pcie->reg_base = devm_platform_ioremap_resource_byname(pdev, "reg");
>  	if (IS_ERR(pcie->reg_base)) {
>  		dev_err(dev, "missing \"reg\"\n");
>  		return PTR_ERR(pcie->reg_base);
> diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
> index 8c2543f28ba0..dcc460a54875 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence-host.c
> +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
> @@ -225,8 +225,7 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
>  	rc->device_id = 0xffff;
>  	of_property_read_u32(np, "device-id", &rc->device_id);
>  
> -	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
> -	pcie->reg_base = devm_ioremap_resource(dev, res);
> +	pcie->reg_base = devm_platform_ioremap_resource_byname(pdev, "reg");
>  	if (IS_ERR(pcie->reg_base)) {
>  		dev_err(dev, "missing \"reg\"\n");
>  		return PTR_ERR(pcie->reg_base);
> diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
> index e3e917243e10..3e608383df66 100644
> --- a/drivers/pci/controller/pci-tegra.c
> +++ b/drivers/pci/controller/pci-tegra.c
> @@ -1462,7 +1462,7 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
>  {
>  	struct device *dev = pcie->dev;
>  	struct platform_device *pdev = to_platform_device(dev);
> -	struct resource *pads, *afi, *res;
> +	struct resource *res;
>  	const struct tegra_pcie_soc *soc = pcie->soc;
>  	int err;
>  
> @@ -1486,15 +1486,13 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
>  		}
>  	}
>  
> -	pads = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pads");
> -	pcie->pads = devm_ioremap_resource(dev, pads);
> +	pcie->pads = devm_platform_ioremap_resource_byname(pdev, "pads");
>  	if (IS_ERR(pcie->pads)) {
>  		err = PTR_ERR(pcie->pads);
>  		goto phys_put;
>  	}
>  
> -	afi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "afi");
> -	pcie->afi = devm_ioremap_resource(dev, afi);
> +	pcie->afi = devm_platform_ioremap_resource_byname(pdev, "afi");
>  	if (IS_ERR(pcie->afi)) {
>  		err = PTR_ERR(pcie->afi);
>  		goto phys_put;
> diff --git a/drivers/pci/controller/pci-xgene.c b/drivers/pci/controller/pci-xgene.c
> index d1efa8ffbae1..1431a18eb02c 100644
> --- a/drivers/pci/controller/pci-xgene.c
> +++ b/drivers/pci/controller/pci-xgene.c
> @@ -355,8 +355,7 @@ static int xgene_pcie_map_reg(struct xgene_pcie_port *port,
>  	if (IS_ERR(port->csr_base))
>  		return PTR_ERR(port->csr_base);
>  
> -	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
> -	port->cfg_base = devm_ioremap_resource(dev, res);
> +	port->cfg_base = devm_platform_ioremap_resource_byname(pdev, "cfg");
>  	if (IS_ERR(port->cfg_base))
>  		return PTR_ERR(port->cfg_base);
>  	port->cfg_addr = res->start;
> diff --git a/drivers/pci/controller/pcie-altera-msi.c b/drivers/pci/controller/pcie-altera-msi.c
> index 16d938920ca5..613e19af71bd 100644
> --- a/drivers/pci/controller/pcie-altera-msi.c
> +++ b/drivers/pci/controller/pcie-altera-msi.c
> @@ -228,8 +228,7 @@ static int altera_msi_probe(struct platform_device *pdev)
>  	mutex_init(&msi->lock);
>  	msi->pdev = pdev;
>  
> -	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csr");
> -	msi->csr_base = devm_ioremap_resource(&pdev->dev, res);
> +	msi->csr_base = devm_platform_ioremap_resource_byname(pdev, "csr");
>  	if (IS_ERR(msi->csr_base)) {
>  		dev_err(&pdev->dev, "failed to map csr memory\n");
>  		return PTR_ERR(msi->csr_base);
> diff --git a/drivers/pci/controller/pcie-altera.c b/drivers/pci/controller/pcie-altera.c
> index 24cb1c331058..7200e40ffa26 100644
> --- a/drivers/pci/controller/pcie-altera.c
> +++ b/drivers/pci/controller/pcie-altera.c
> @@ -696,17 +696,14 @@ static int altera_pcie_parse_dt(struct altera_pcie *pcie)
>  {
>  	struct device *dev = &pcie->pdev->dev;
>  	struct platform_device *pdev = pcie->pdev;
> -	struct resource *cra;
> -	struct resource *hip;
>  
> -	cra = platform_get_resource_byname(pdev, IORESOURCE_MEM, "Cra");
> -	pcie->cra_base = devm_ioremap_resource(dev, cra);
> +	pcie->cra_base = devm_platform_ioremap_resource_byname(pdev, "Cra");
>  	if (IS_ERR(pcie->cra_base))
>  		return PTR_ERR(pcie->cra_base);
>  
>  	if (pcie->pcie_data->version == ALTERA_PCIE_V2) {
> -		hip = platform_get_resource_byname(pdev, IORESOURCE_MEM, "Hip");
> -		pcie->hip_base = devm_ioremap_resource(&pdev->dev, hip);
> +		pcie->hip_base =
> +			devm_platform_ioremap_resource_byname(pdev, "Hip");
>  		if (IS_ERR(pcie->hip_base))
>  			return PTR_ERR(pcie->hip_base);
>  	}
> diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
> index ebfa7d5a4e2d..d8e38276dbe3 100644
> --- a/drivers/pci/controller/pcie-mediatek.c
> +++ b/drivers/pci/controller/pcie-mediatek.c
> @@ -905,7 +905,6 @@ static int mtk_pcie_parse_port(struct mtk_pcie *pcie,
>  			       int slot)
>  {
>  	struct mtk_pcie_port *port;
> -	struct resource *regs;
>  	struct device *dev = pcie->dev;
>  	struct platform_device *pdev = to_platform_device(dev);
>  	char name[10];
> @@ -916,8 +915,7 @@ static int mtk_pcie_parse_port(struct mtk_pcie *pcie,
>  		return -ENOMEM;
>  
>  	snprintf(name, sizeof(name), "port%d", slot);
> -	regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
> -	port->base = devm_ioremap_resource(dev, regs);
> +	port->base = devm_platform_ioremap_resource_byname(pdev, name);
>  	if (IS_ERR(port->base)) {
>  		dev_err(dev, "failed to map port%d base\n", slot);
>  		return PTR_ERR(port->base);
> diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c
> index c53d1322a3d6..904dec0d3a88 100644
> --- a/drivers/pci/controller/pcie-rockchip.c
> +++ b/drivers/pci/controller/pcie-rockchip.c
> @@ -45,9 +45,8 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
>  			return -EINVAL;
>  	}
>  
> -	regs = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> -					    "apb-base");
> -	rockchip->apb_base = devm_ioremap_resource(dev, regs);
> +	rockchip->apb_base =
> +		devm_platform_ioremap_resource_byname(pdev, "apb-base");
>  	if (IS_ERR(rockchip->apb_base))
>  		return PTR_ERR(rockchip->apb_base);
>  
> -- 
> 2.25.0
> 

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH v2] PCI: controller: convert to devm_platform_ioremap_resource_byname()
  2020-07-07 11:31 ` Lorenzo Pieralisi
@ 2020-07-07 11:40   ` Lorenzo Pieralisi
  0 siblings, 0 replies; 5+ messages in thread
From: Lorenzo Pieralisi @ 2020-07-07 11:40 UTC (permalink / raw)
  To: Dejin Zheng
  Cc: tjoseph, robh, bhelgaas, thierry.reding, toan, ley.foon.tan,
	shawn.lin, linux-pci, linux-kernel

On Tue, Jul 07, 2020 at 12:31:17PM +0100, Lorenzo Pieralisi wrote:
> On Wed, Jun 03, 2020 at 01:16:01AM +0800, Dejin Zheng wrote:
> > Use devm_platform_ioremap_resource_byname() to simplify codes.
> > it contains platform_get_resource_byname() and devm_ioremap_resource().
> > 
> > Signed-off-by: Dejin Zheng <zhengdejin5@gmail.com>
> > ---
> > v1 -> v2:
> > 	- Discard changes to the file drivers/pci/controller/pcie-xilinx-nwl.c
> > 	  Due to my mistakes, my patch will modify pcie-xilinx-nwl.c,
> > 	  but it still need to use the res variable, but
> > 	  devm_platform_ioremap_resource_byname() funtion can't assign a
> > 	  value to the variable res. kbuild test robot report it. Thanks
> > 	  very much for kbuild test robot <lkp@intel.com>.
> > 
> >  drivers/pci/controller/cadence/pcie-cadence-ep.c   | 3 +--
> >  drivers/pci/controller/cadence/pcie-cadence-host.c | 3 +--
> >  drivers/pci/controller/pci-tegra.c                 | 8 +++-----
> >  drivers/pci/controller/pci-xgene.c                 | 3 +--
> >  drivers/pci/controller/pcie-altera-msi.c           | 3 +--
> >  drivers/pci/controller/pcie-altera.c               | 9 +++------
> >  drivers/pci/controller/pcie-mediatek.c             | 4 +---
> >  drivers/pci/controller/pcie-rockchip.c             | 5 ++---
> >  8 files changed, 13 insertions(+), 25 deletions(-)
> 
> Applied to pci/dwc with Rob and Gustavo's tags (next time please
> carry them over and send v2 in-reply-to v1 so that I can follow
> it), thanks.

Moved to pci/misc since it is not really dwc related, apologies.

Lorenzo

> Lorenzo
> 
> > diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c
> > index 1c15c8352125..74ffa03fde5f 100644
> > --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c
> > +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c
> > @@ -408,8 +408,7 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)
> >  
> >  	pcie->is_rc = false;
> >  
> > -	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
> > -	pcie->reg_base = devm_ioremap_resource(dev, res);
> > +	pcie->reg_base = devm_platform_ioremap_resource_byname(pdev, "reg");
> >  	if (IS_ERR(pcie->reg_base)) {
> >  		dev_err(dev, "missing \"reg\"\n");
> >  		return PTR_ERR(pcie->reg_base);
> > diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
> > index 8c2543f28ba0..dcc460a54875 100644
> > --- a/drivers/pci/controller/cadence/pcie-cadence-host.c
> > +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
> > @@ -225,8 +225,7 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
> >  	rc->device_id = 0xffff;
> >  	of_property_read_u32(np, "device-id", &rc->device_id);
> >  
> > -	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
> > -	pcie->reg_base = devm_ioremap_resource(dev, res);
> > +	pcie->reg_base = devm_platform_ioremap_resource_byname(pdev, "reg");
> >  	if (IS_ERR(pcie->reg_base)) {
> >  		dev_err(dev, "missing \"reg\"\n");
> >  		return PTR_ERR(pcie->reg_base);
> > diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
> > index e3e917243e10..3e608383df66 100644
> > --- a/drivers/pci/controller/pci-tegra.c
> > +++ b/drivers/pci/controller/pci-tegra.c
> > @@ -1462,7 +1462,7 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
> >  {
> >  	struct device *dev = pcie->dev;
> >  	struct platform_device *pdev = to_platform_device(dev);
> > -	struct resource *pads, *afi, *res;
> > +	struct resource *res;
> >  	const struct tegra_pcie_soc *soc = pcie->soc;
> >  	int err;
> >  
> > @@ -1486,15 +1486,13 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
> >  		}
> >  	}
> >  
> > -	pads = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pads");
> > -	pcie->pads = devm_ioremap_resource(dev, pads);
> > +	pcie->pads = devm_platform_ioremap_resource_byname(pdev, "pads");
> >  	if (IS_ERR(pcie->pads)) {
> >  		err = PTR_ERR(pcie->pads);
> >  		goto phys_put;
> >  	}
> >  
> > -	afi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "afi");
> > -	pcie->afi = devm_ioremap_resource(dev, afi);
> > +	pcie->afi = devm_platform_ioremap_resource_byname(pdev, "afi");
> >  	if (IS_ERR(pcie->afi)) {
> >  		err = PTR_ERR(pcie->afi);
> >  		goto phys_put;
> > diff --git a/drivers/pci/controller/pci-xgene.c b/drivers/pci/controller/pci-xgene.c
> > index d1efa8ffbae1..1431a18eb02c 100644
> > --- a/drivers/pci/controller/pci-xgene.c
> > +++ b/drivers/pci/controller/pci-xgene.c
> > @@ -355,8 +355,7 @@ static int xgene_pcie_map_reg(struct xgene_pcie_port *port,
> >  	if (IS_ERR(port->csr_base))
> >  		return PTR_ERR(port->csr_base);
> >  
> > -	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
> > -	port->cfg_base = devm_ioremap_resource(dev, res);
> > +	port->cfg_base = devm_platform_ioremap_resource_byname(pdev, "cfg");
> >  	if (IS_ERR(port->cfg_base))
> >  		return PTR_ERR(port->cfg_base);
> >  	port->cfg_addr = res->start;
> > diff --git a/drivers/pci/controller/pcie-altera-msi.c b/drivers/pci/controller/pcie-altera-msi.c
> > index 16d938920ca5..613e19af71bd 100644
> > --- a/drivers/pci/controller/pcie-altera-msi.c
> > +++ b/drivers/pci/controller/pcie-altera-msi.c
> > @@ -228,8 +228,7 @@ static int altera_msi_probe(struct platform_device *pdev)
> >  	mutex_init(&msi->lock);
> >  	msi->pdev = pdev;
> >  
> > -	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csr");
> > -	msi->csr_base = devm_ioremap_resource(&pdev->dev, res);
> > +	msi->csr_base = devm_platform_ioremap_resource_byname(pdev, "csr");
> >  	if (IS_ERR(msi->csr_base)) {
> >  		dev_err(&pdev->dev, "failed to map csr memory\n");
> >  		return PTR_ERR(msi->csr_base);
> > diff --git a/drivers/pci/controller/pcie-altera.c b/drivers/pci/controller/pcie-altera.c
> > index 24cb1c331058..7200e40ffa26 100644
> > --- a/drivers/pci/controller/pcie-altera.c
> > +++ b/drivers/pci/controller/pcie-altera.c
> > @@ -696,17 +696,14 @@ static int altera_pcie_parse_dt(struct altera_pcie *pcie)
> >  {
> >  	struct device *dev = &pcie->pdev->dev;
> >  	struct platform_device *pdev = pcie->pdev;
> > -	struct resource *cra;
> > -	struct resource *hip;
> >  
> > -	cra = platform_get_resource_byname(pdev, IORESOURCE_MEM, "Cra");
> > -	pcie->cra_base = devm_ioremap_resource(dev, cra);
> > +	pcie->cra_base = devm_platform_ioremap_resource_byname(pdev, "Cra");
> >  	if (IS_ERR(pcie->cra_base))
> >  		return PTR_ERR(pcie->cra_base);
> >  
> >  	if (pcie->pcie_data->version == ALTERA_PCIE_V2) {
> > -		hip = platform_get_resource_byname(pdev, IORESOURCE_MEM, "Hip");
> > -		pcie->hip_base = devm_ioremap_resource(&pdev->dev, hip);
> > +		pcie->hip_base =
> > +			devm_platform_ioremap_resource_byname(pdev, "Hip");
> >  		if (IS_ERR(pcie->hip_base))
> >  			return PTR_ERR(pcie->hip_base);
> >  	}
> > diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
> > index ebfa7d5a4e2d..d8e38276dbe3 100644
> > --- a/drivers/pci/controller/pcie-mediatek.c
> > +++ b/drivers/pci/controller/pcie-mediatek.c
> > @@ -905,7 +905,6 @@ static int mtk_pcie_parse_port(struct mtk_pcie *pcie,
> >  			       int slot)
> >  {
> >  	struct mtk_pcie_port *port;
> > -	struct resource *regs;
> >  	struct device *dev = pcie->dev;
> >  	struct platform_device *pdev = to_platform_device(dev);
> >  	char name[10];
> > @@ -916,8 +915,7 @@ static int mtk_pcie_parse_port(struct mtk_pcie *pcie,
> >  		return -ENOMEM;
> >  
> >  	snprintf(name, sizeof(name), "port%d", slot);
> > -	regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
> > -	port->base = devm_ioremap_resource(dev, regs);
> > +	port->base = devm_platform_ioremap_resource_byname(pdev, name);
> >  	if (IS_ERR(port->base)) {
> >  		dev_err(dev, "failed to map port%d base\n", slot);
> >  		return PTR_ERR(port->base);
> > diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c
> > index c53d1322a3d6..904dec0d3a88 100644
> > --- a/drivers/pci/controller/pcie-rockchip.c
> > +++ b/drivers/pci/controller/pcie-rockchip.c
> > @@ -45,9 +45,8 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
> >  			return -EINVAL;
> >  	}
> >  
> > -	regs = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> > -					    "apb-base");
> > -	rockchip->apb_base = devm_ioremap_resource(dev, regs);
> > +	rockchip->apb_base =
> > +		devm_platform_ioremap_resource_byname(pdev, "apb-base");
> >  	if (IS_ERR(rockchip->apb_base))
> >  		return PTR_ERR(rockchip->apb_base);
> >  
> > -- 
> > 2.25.0
> > 

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH v2] PCI: controller: convert to devm_platform_ioremap_resource_byname()
  2020-06-02 17:16 [PATCH v2] PCI: controller: convert to devm_platform_ioremap_resource_byname() Dejin Zheng
  2020-07-07 11:31 ` Lorenzo Pieralisi
@ 2021-03-27 18:02 ` dann frazier
  2021-03-28 13:49   ` Dejin Zheng
  1 sibling, 1 reply; 5+ messages in thread
From: dann frazier @ 2021-03-27 18:02 UTC (permalink / raw)
  To: Dejin Zheng
  Cc: tjoseph, lorenzo.pieralisi, robh, bhelgaas, thierry.reding, toan,
	ley.foon.tan, shawn.lin, linux-pci, linux-kernel

On Wed, Jun 03, 2020 at 01:16:01AM +0800, Dejin Zheng wrote:
> Use devm_platform_ioremap_resource_byname() to simplify codes.
> it contains platform_get_resource_byname() and devm_ioremap_resource().
> 
> Signed-off-by: Dejin Zheng <zhengdejin5@gmail.com>
> ---
> v1 -> v2:
> 	- Discard changes to the file drivers/pci/controller/pcie-xilinx-nwl.c
> 	  Due to my mistakes, my patch will modify pcie-xilinx-nwl.c,
> 	  but it still need to use the res variable, but
> 	  devm_platform_ioremap_resource_byname() funtion can't assign a
> 	  value to the variable res. kbuild test robot report it. Thanks
> 	  very much for kbuild test robot <lkp@intel.com>.
> 
>  drivers/pci/controller/cadence/pcie-cadence-ep.c   | 3 +--
>  drivers/pci/controller/cadence/pcie-cadence-host.c | 3 +--
>  drivers/pci/controller/pci-tegra.c                 | 8 +++-----
>  drivers/pci/controller/pci-xgene.c                 | 3 +--
>  drivers/pci/controller/pcie-altera-msi.c           | 3 +--
>  drivers/pci/controller/pcie-altera.c               | 9 +++------
>  drivers/pci/controller/pcie-mediatek.c             | 4 +---
>  drivers/pci/controller/pcie-rockchip.c             | 5 ++---
>  8 files changed, 13 insertions(+), 25 deletions(-)
> 

hey,
  I found that recent kernels fail to initialize PCI devices on our HP
m400 Moonshot cartridges, which are based on the X-Gene SoC. I
bisected the issue down to this commit. I found that just reverting
this hunk in pci-xgene.c is enough to get v5.12 rcs booting again:

> diff --git a/drivers/pci/controller/pci-xgene.c b/drivers/pci/controller/pci-xgene.c
> index d1efa8ffbae1..1431a18eb02c 100644
> --- a/drivers/pci/controller/pci-xgene.c
> +++ b/drivers/pci/controller/pci-xgene.c
> @@ -355,8 +355,7 @@ static int xgene_pcie_map_reg(struct xgene_pcie_port *port,
>  	if (IS_ERR(port->csr_base))
>  		return PTR_ERR(port->csr_base);
>  
> -	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
> -	port->cfg_base = devm_ioremap_resource(dev, res);
> +	port->cfg_base = devm_platform_ioremap_resource_byname(pdev, "cfg");
>  	if (IS_ERR(port->cfg_base))
>  		return PTR_ERR(port->cfg_base);
>  	port->cfg_addr = res->start;


In case it helps, here's the PCI initialization portion of dmesg when
it fails:

[    0.756359] xgene-pcie 1f500000.pcie: host bridge /soc/pcie@1f500000 ranges:
[    0.756372] xgene-pcie 1f500000.pcie:   No bus range found for /soc/pcie@1f500000, using [bus 00-ff]
[    0.756387] xgene-pcie 1f500000.pcie:      MEM 0xa130000000..0xa1afffffff -> 0x0030000000
[    0.756404] xgene-pcie 1f500000.pcie:   IB MEM 0x4000000000..0x7fffffffff -> 0x4000000000
[    0.756459] xgene-pcie 1f500000.pcie: (rc) x8 gen-2 link up
[    0.756525] xgene-pcie 1f500000.pcie: PCI host bridge to bus 0000:00
[    0.756532] pci_bus 0000:00: root bus resource [bus 00-ff]
[    0.756538] pci_bus 0000:00: root bus resource [mem 0xa130000000-0xa1afffffff] (bus address [0x30000000-0xafffffff])


and here's what it looks like when it works:

[    0.756793] xgene-pcie 1f500000.pcie: host bridge /soc/pcie@1f500000 ranges:
[    0.756807] xgene-pcie 1f500000.pcie:   No bus range found for /soc/pcie@1f500000, using [bus 00-ff]
[    0.756822] xgene-pcie 1f500000.pcie:      MEM 0xa130000000..0xa1afffffff -> 0x0030000000
[    0.756838] xgene-pcie 1f500000.pcie:   IB MEM 0x4000000000..0x7fffffffff -> 0x4000000000
[    0.756892] xgene-pcie 1f500000.pcie: (rc) x8 gen-2 link up
[    0.756962] xgene-pcie 1f500000.pcie: PCI host bridge to bus 0000:00
[    0.756968] pci_bus 0000:00: root bus resource [bus 00-ff]
[    0.756974] pci_bus 0000:00: root bus resource [mem 0xa130000000-0xa1afffffff] (bus address [0x30000000-0xafffffff])
[    0.757006] pci 0000:00:00.0: [10e8:e004] type 01 class 0x060400
[    0.757014] pci_bus 0000:00: 2-byte config write to 0000:00:00.0 offset 0x4 may corrupt adjacent RW1C bits
[    0.757022] pci_bus 0000:00: 2-byte config write to 0000:00:00.0 offset 0x4 may corrupt adjacent RW1C bits
[    0.757032] pci_bus 0000:00: 2-byte config write to 0000:00:00.0 offset 0x4 may corrupt adjacent RW1C bits
[    0.757039] pci_bus 0000:00: 2-byte config write to 0000:00:00.0 offset 0x4 may corrupt adjacent RW1C bits
[    0.757046] pci_bus 0000:00: 2-byte config write to 0000:00:00.0 offset 0x4 may corrupt adjacent RW1C bits
[    0.757052] pci_bus 0000:00: 2-byte config write to 0000:00:00.0 offset 0x4 may corrupt adjacent RW1C bits
[    0.757059] pci_bus 0000:00: 2-byte config write to 0000:00:00.0 offset 0x4 may corrupt adjacent RW1C bits
[    0.757068] pci_bus 0000:00: 2-byte config write to 0000:00:00.0 offset 0x4 may corrupt adjacent RW1C bits
[    0.757094] pci_bus 0000:00: 2-byte config write to 0000:00:00.0 offset 0x3e may corrupt adjacent RW1C bits
[    0.757143] pci 0000:00:00.0: supports D1 D2
[    0.757589] pci_bus 0000:00: 2-byte config write to 0000:00:00.0 offset 0x3e may corrupt adjacent RW1C bits
[    0.757968] pci 0000:01:00.0: [15b3:1007] type 00 class 0x020000
[    0.758381] pci 0000:01:00.0: reg 0x10: [mem 0x00100000-0x001fffff 64bit]
[    0.758642] pci 0000:01:00.0: reg 0x18: [mem 0x00800000-0x00ffffff 64bit pref]
[    0.761110] pci 0000:01:00.0: reg 0x134: [mem 0x00000000-0x007fffff 64bit pref]
[    0.761115] pci 0000:01:00.0: VF(n) BAR2 space: [mem 0x00000000-0x03ffffff 64bit pref] (contains BAR2 for 8 VFs)
[    0.762921] pci 0000:01:00.0: 32.000 Gb/s available PCIe bandwidth, limited by 5.0 GT/s PCIe x8 link at 0000:00:00.0 (capable of 63.008 Gb/s with 8.0 GT/s PCIe x8 link)
[    0.773939] pci 0000:00:00.0: BAR 15: assigned [mem 0xa130000000-0xa1347fffff 64bit pref]
[    0.773947] pci 0000:00:00.0: BAR 14: assigned [mem 0xa134800000-0xa1348fffff]
[    0.773954] pci 0000:01:00.0: BAR 2: assigned [mem 0xa130000000-0xa1307fffff 64bit pref]
[    0.774136] pci 0000:01:00.0: BAR 9: assigned [mem 0xa130800000-0xa1347fffff 64bit pref]
[    0.774203] pci 0000:01:00.0: BAR 0: assigned [mem 0xa134800000-0xa1348fffff 64bit]
[    0.774384] pci 0000:00:00.0: PCI bridge to [bus 01]
[    0.774391] pci 0000:00:00.0:   bridge window [mem 0xa134800000-0xa1348fffff]
[    0.774397] pci 0000:00:00.0:   bridge window [mem 0xa130000000-0xa1347fffff 64bit pref]
[    0.774576] pcieport 0000:00:00.0: PME: Signaling with IRQ 89
[    0.774734] pcieport 0000:00:00.0: AER: enabled with IRQ 89


  -dann

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH v2] PCI: controller: convert to devm_platform_ioremap_resource_byname()
  2021-03-27 18:02 ` dann frazier
@ 2021-03-28 13:49   ` Dejin Zheng
  0 siblings, 0 replies; 5+ messages in thread
From: Dejin Zheng @ 2021-03-28 13:49 UTC (permalink / raw)
  To: dann frazier
  Cc: tjoseph, lorenzo.pieralisi, robh, bhelgaas, thierry.reding, toan,
	ley.foon.tan, shawn.lin, linux-pci, linux-kernel

On Sat, Mar 27, 2021 at 12:02:42PM -0600, dann frazier wrote:
Hi Dann,

I'm so sorry for that, And there is a mistake with my patch that caused
this problem. Thank you very much for telling me this, I will fix it as
soon as possible.

> On Wed, Jun 03, 2020 at 01:16:01AM +0800, Dejin Zheng wrote:
> > Use devm_platform_ioremap_resource_byname() to simplify codes.
> > it contains platform_get_resource_byname() and devm_ioremap_resource().
> > 
> > Signed-off-by: Dejin Zheng <zhengdejin5@gmail.com>
> > ---
> > v1 -> v2:
> > 	- Discard changes to the file drivers/pci/controller/pcie-xilinx-nwl.c
> > 	  Due to my mistakes, my patch will modify pcie-xilinx-nwl.c,
> > 	  but it still need to use the res variable, but
> > 	  devm_platform_ioremap_resource_byname() funtion can't assign a
> > 	  value to the variable res. kbuild test robot report it. Thanks
> > 	  very much for kbuild test robot <lkp@intel.com>.
> > 
> >  drivers/pci/controller/cadence/pcie-cadence-ep.c   | 3 +--
> >  drivers/pci/controller/cadence/pcie-cadence-host.c | 3 +--
> >  drivers/pci/controller/pci-tegra.c                 | 8 +++-----
> >  drivers/pci/controller/pci-xgene.c                 | 3 +--
> >  drivers/pci/controller/pcie-altera-msi.c           | 3 +--
> >  drivers/pci/controller/pcie-altera.c               | 9 +++------
> >  drivers/pci/controller/pcie-mediatek.c             | 4 +---
> >  drivers/pci/controller/pcie-rockchip.c             | 5 ++---
> >  8 files changed, 13 insertions(+), 25 deletions(-)
> > 
> 
> hey,
>   I found that recent kernels fail to initialize PCI devices on our HP
> m400 Moonshot cartridges, which are based on the X-Gene SoC. I
> bisected the issue down to this commit. I found that just reverting
> this hunk in pci-xgene.c is enough to get v5.12 rcs booting again:
> 
> > diff --git a/drivers/pci/controller/pci-xgene.c b/drivers/pci/controller/pci-xgene.c
> > index d1efa8ffbae1..1431a18eb02c 100644
> > --- a/drivers/pci/controller/pci-xgene.c
> > +++ b/drivers/pci/controller/pci-xgene.c
> > @@ -355,8 +355,7 @@ static int xgene_pcie_map_reg(struct xgene_pcie_port *port,
> >  	if (IS_ERR(port->csr_base))
> >  		return PTR_ERR(port->csr_base);
> >  
> > -	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
> > -	port->cfg_base = devm_ioremap_resource(dev, res);
> > +	port->cfg_base = devm_platform_ioremap_resource_byname(pdev, "cfg");
> >  	if (IS_ERR(port->cfg_base))
> >  		return PTR_ERR(port->cfg_base);
> >  	port->cfg_addr = res->start;
The mistake of this patch is here, port->cfg_addr need the res->start,
But this patch remove the res of get "cfg" resource. here use the wrong
data by get "csr" resource in the previous.

BR,
Dejin
> 
> 
> In case it helps, here's the PCI initialization portion of dmesg when
> it fails:
> 
> [    0.756359] xgene-pcie 1f500000.pcie: host bridge /soc/pcie@1f500000 ranges:
> [    0.756372] xgene-pcie 1f500000.pcie:   No bus range found for /soc/pcie@1f500000, using [bus 00-ff]
> [    0.756387] xgene-pcie 1f500000.pcie:      MEM 0xa130000000..0xa1afffffff -> 0x0030000000
> [    0.756404] xgene-pcie 1f500000.pcie:   IB MEM 0x4000000000..0x7fffffffff -> 0x4000000000
> [    0.756459] xgene-pcie 1f500000.pcie: (rc) x8 gen-2 link up
> [    0.756525] xgene-pcie 1f500000.pcie: PCI host bridge to bus 0000:00
> [    0.756532] pci_bus 0000:00: root bus resource [bus 00-ff]
> [    0.756538] pci_bus 0000:00: root bus resource [mem 0xa130000000-0xa1afffffff] (bus address [0x30000000-0xafffffff])
> 
> 
> and here's what it looks like when it works:
> 
> [    0.756793] xgene-pcie 1f500000.pcie: host bridge /soc/pcie@1f500000 ranges:
> [    0.756807] xgene-pcie 1f500000.pcie:   No bus range found for /soc/pcie@1f500000, using [bus 00-ff]
> [    0.756822] xgene-pcie 1f500000.pcie:      MEM 0xa130000000..0xa1afffffff -> 0x0030000000
> [    0.756838] xgene-pcie 1f500000.pcie:   IB MEM 0x4000000000..0x7fffffffff -> 0x4000000000
> [    0.756892] xgene-pcie 1f500000.pcie: (rc) x8 gen-2 link up
> [    0.756962] xgene-pcie 1f500000.pcie: PCI host bridge to bus 0000:00
> [    0.756968] pci_bus 0000:00: root bus resource [bus 00-ff]
> [    0.756974] pci_bus 0000:00: root bus resource [mem 0xa130000000-0xa1afffffff] (bus address [0x30000000-0xafffffff])
> [    0.757006] pci 0000:00:00.0: [10e8:e004] type 01 class 0x060400
> [    0.757014] pci_bus 0000:00: 2-byte config write to 0000:00:00.0 offset 0x4 may corrupt adjacent RW1C bits
> [    0.757022] pci_bus 0000:00: 2-byte config write to 0000:00:00.0 offset 0x4 may corrupt adjacent RW1C bits
> [    0.757032] pci_bus 0000:00: 2-byte config write to 0000:00:00.0 offset 0x4 may corrupt adjacent RW1C bits
> [    0.757039] pci_bus 0000:00: 2-byte config write to 0000:00:00.0 offset 0x4 may corrupt adjacent RW1C bits
> [    0.757046] pci_bus 0000:00: 2-byte config write to 0000:00:00.0 offset 0x4 may corrupt adjacent RW1C bits
> [    0.757052] pci_bus 0000:00: 2-byte config write to 0000:00:00.0 offset 0x4 may corrupt adjacent RW1C bits
> [    0.757059] pci_bus 0000:00: 2-byte config write to 0000:00:00.0 offset 0x4 may corrupt adjacent RW1C bits
> [    0.757068] pci_bus 0000:00: 2-byte config write to 0000:00:00.0 offset 0x4 may corrupt adjacent RW1C bits
> [    0.757094] pci_bus 0000:00: 2-byte config write to 0000:00:00.0 offset 0x3e may corrupt adjacent RW1C bits
> [    0.757143] pci 0000:00:00.0: supports D1 D2
> [    0.757589] pci_bus 0000:00: 2-byte config write to 0000:00:00.0 offset 0x3e may corrupt adjacent RW1C bits
> [    0.757968] pci 0000:01:00.0: [15b3:1007] type 00 class 0x020000
> [    0.758381] pci 0000:01:00.0: reg 0x10: [mem 0x00100000-0x001fffff 64bit]
> [    0.758642] pci 0000:01:00.0: reg 0x18: [mem 0x00800000-0x00ffffff 64bit pref]
> [    0.761110] pci 0000:01:00.0: reg 0x134: [mem 0x00000000-0x007fffff 64bit pref]
> [    0.761115] pci 0000:01:00.0: VF(n) BAR2 space: [mem 0x00000000-0x03ffffff 64bit pref] (contains BAR2 for 8 VFs)
> [    0.762921] pci 0000:01:00.0: 32.000 Gb/s available PCIe bandwidth, limited by 5.0 GT/s PCIe x8 link at 0000:00:00.0 (capable of 63.008 Gb/s with 8.0 GT/s PCIe x8 link)
> [    0.773939] pci 0000:00:00.0: BAR 15: assigned [mem 0xa130000000-0xa1347fffff 64bit pref]
> [    0.773947] pci 0000:00:00.0: BAR 14: assigned [mem 0xa134800000-0xa1348fffff]
> [    0.773954] pci 0000:01:00.0: BAR 2: assigned [mem 0xa130000000-0xa1307fffff 64bit pref]
> [    0.774136] pci 0000:01:00.0: BAR 9: assigned [mem 0xa130800000-0xa1347fffff 64bit pref]
> [    0.774203] pci 0000:01:00.0: BAR 0: assigned [mem 0xa134800000-0xa1348fffff 64bit]
> [    0.774384] pci 0000:00:00.0: PCI bridge to [bus 01]
> [    0.774391] pci 0000:00:00.0:   bridge window [mem 0xa134800000-0xa1348fffff]
> [    0.774397] pci 0000:00:00.0:   bridge window [mem 0xa130000000-0xa1347fffff 64bit pref]
> [    0.774576] pcieport 0000:00:00.0: PME: Signaling with IRQ 89
> [    0.774734] pcieport 0000:00:00.0: AER: enabled with IRQ 89
> 
> 
>   -dann

^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2021-03-28 13:50 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-06-02 17:16 [PATCH v2] PCI: controller: convert to devm_platform_ioremap_resource_byname() Dejin Zheng
2020-07-07 11:31 ` Lorenzo Pieralisi
2020-07-07 11:40   ` Lorenzo Pieralisi
2021-03-27 18:02 ` dann frazier
2021-03-28 13:49   ` Dejin Zheng

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