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From: Bjorn Helgaas <helgaas@kernel.org>
To: Yicong Yang <yangyicong@hisilicon.com>
Cc: linux-pci@vger.kernel.org,
	sathyanarayanan.kuppuswamy@linux.intel.com, kbusch@kernel.org,
	sean.v.kelley@intel.com, qiuxu.zhuo@intel.com,
	prime.zeng@huawei.com, linuxarm@openeuler.org
Subject: Re: [PATCH] PCI/DPC: Disable ERR_COR explicitly for native dpc service
Date: Sat, 10 Apr 2021 10:21:03 -0500	[thread overview]
Message-ID: <20210410152103.GA2043340@bjorn-Precision-5520> (raw)
In-Reply-To: <1612356795-32505-2-git-send-email-yangyicong@hisilicon.com>

On Wed, Feb 03, 2021 at 08:53:15PM +0800, Yicong Yang wrote:
> Per Downstream Port Containment Related Enhancements ECN[1],
> Table 4-6 Interpretation of _OSC Control Field Returned Value,
> for bit 7 of _OSC control return value:
> 
>   "If firmware allows the OS control of this feature, then,
>   in the context of the _OSC method the OS must ensure that
>   Downstream Port Containment ERR_COR signaling is disabled
>   as described in the PCI Express Base Specification."
> 
> and PCI Express Base Specification Revision 4.0 Version 1.0
> section 6.2.10.2, Use of DPC ERR_COR Signaling:
> 
>   "...DPC ERR_COR signaling is primarily intended for use by
>   platform firmware..."
> 
> Currently we don't set DPC ERR_COR enable bit, but explicitly
> clear the bit to ensure it's disabled.
> 
> [1] Downstream Port Containment Related Enhancements ECN,
>     Jan 28, 2019, affecting PCI Firmware Specification, Rev. 3.2
>     https://members.pcisig.com/wg/PCI-SIG/document/12888
> 
> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>

Anybody want to chime in and review this?  Sometimes I feel like a
one-man band :)

> ---
>  drivers/pci/pcie/dpc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/pcie/dpc.c b/drivers/pci/pcie/dpc.c
> index e05aba8..5cc8ef3 100644
> --- a/drivers/pci/pcie/dpc.c
> +++ b/drivers/pci/pcie/dpc.c
> @@ -302,7 +302,7 @@ static int dpc_probe(struct pcie_device *dev)
>  	pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CAP, &cap);
>  	pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, &ctl);
>  
> -	ctl = (ctl & 0xfff4) | PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN;
> +	ctl = (ctl & 0xffe4) | PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN;
>  	pci_write_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, ctl);
>  	pci_info(pdev, "enabled with IRQ %d\n", dev->irq);
>  
> -- 
> 2.8.1
> 

  parent reply	other threads:[~2021-04-10 15:21 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-03 12:53 [PATCH v2] PCI/DPC: Check host->native_dpc before enable dpc service Yicong Yang
2021-02-03 12:53 ` [PATCH] PCI/DPC: Disable ERR_COR explicitly for native " Yicong Yang
2021-02-18 17:20   ` Bjorn Helgaas
2021-02-24  8:56     ` Yicong Yang
2021-04-10 15:21   ` Bjorn Helgaas [this message]
2021-04-10 19:17     ` Lukas Wunner
2021-04-12  9:32       ` Yicong Yang
2021-04-12  3:32     ` Kuppuswamy, Sathyanarayanan
2021-04-12  9:46       ` Yicong Yang
2021-02-24  9:47 ` [PATCH v2] PCI/DPC: Check host->native_dpc before enable " Yicong Yang
2021-07-26 22:05   ` Bjorn Helgaas
2021-07-28  9:22     ` Yicong Yang

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