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[80.7.220.175]) by smtp.gmail.com with ESMTPSA id f19sm12521084edu.12.2021.04.19.02.07.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 02:07:52 -0700 (PDT) Date: Mon, 19 Apr 2021 10:07:50 +0100 From: Daniel Thompson To: Yicong Yang Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org, linux-pci@vger.kernel.org, alexander.shishkin@linux.intel.com, helgaas@kernel.org, gregkh@linuxfoundation.org, lorenzo.pieralisi@arm.com, will@kernel.org, mark.rutland@arm.com, mathieu.poirier@linaro.org, suzuki.poulose@arm.com, mike.leach@linaro.org, leo.yan@linaro.org, jonathan.cameron@huawei.com, song.bao.hua@hisilicon.com, john.garry@huawei.com, prime.zeng@huawei.com, liuqi115@huawei.com, zhangshaokun@hisilicon.com, linuxarm@huawei.com Subject: Re: [PATCH RESEND 3/4] docs: Add HiSilicon PTT device driver documentation Message-ID: <20210419090750.g6aeyyrki7fiotxl@maple.lan> References: <1618654631-42454-1-git-send-email-yangyicong@hisilicon.com> <1618654631-42454-4-git-send-email-yangyicong@hisilicon.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1618654631-42454-4-git-send-email-yangyicong@hisilicon.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Sat, Apr 17, 2021 at 06:17:10PM +0800, Yicong Yang wrote: > Document the introduction and usage of HiSilicon PTT device driver. > > Signed-off-by: Yicong Yang > --- > Documentation/trace/hisi-ptt.rst | 326 +++++++++++++++++++++++++++++++++++++++ > 1 file changed, 326 insertions(+) > create mode 100644 Documentation/trace/hisi-ptt.rst > > diff --git a/Documentation/trace/hisi-ptt.rst b/Documentation/trace/hisi-ptt.rst > new file mode 100644 > index 0000000..f093846 > --- /dev/null > +++ b/Documentation/trace/hisi-ptt.rst > @@ -0,0 +1,326 @@ > [...] > +On Kunpeng 930 SoC, the PCIe Root Complex is composed of several > +PCIe cores. Each PCIe core includes several Root Ports and a PTT > +RCiEP, like below. The PTT device is capable of tuning and > +tracing the link of the PCIe core. > +:: > + +--------------Core 0-------+ > + | | [ PTT ] | > + | | [Root Port]---[Endpoint] > + | | [Root Port]---[Endpoint] > + | | [Root Port]---[Endpoint] > + Root Complex |------Core 1-------+ > + | | [ PTT ] | > + | | [Root Port]---[ Switch ]---[Endpoint] > + | | [Root Port]---[Endpoint] `-[Endpoint] > + | | [Root Port]---[Endpoint] > + +---------------------------+ > + > +The PTT device driver cannot be loaded if debugfs is not mounted. This can't be right can it? Obviously debugfs must be enabled but why mounted? > +Each PTT device will be presented under /sys/kernel/debugfs/hisi_ptt > +as its root directory, with name of its BDF number. > +:: > + > + /sys/kernel/debug/hisi_ptt/::. > + > +Tune > +==== > + > +PTT tune is designed for monitoring and adjusting PCIe link parameters (events). > +Currently we support events in 4 classes. The scope of the events > +covers the PCIe core to which the PTT device belongs. > + > +Each event is presented as a file under $(PTT root dir)/$(BDF)/tune, and > +mostly a simple open/read/write/close cycle will be used to tune > +the event. > +:: > + $ cd /sys/kernel/debug/hisi_ptt/$(BDF)/tune > + $ ls > + qos_tx_cpl qos_tx_np qos_tx_p > + tx_path_rx_req_alloc_buf_level > + tx_path_tx_req_alloc_buf_level > + $ cat qos_tx_dp > + 1 > + $ echo 2 > qos_tx_dp > + $ cat qos_tx_dp > + 2 > + > +Current value (numerical value) of the event can be simply read > +from the file, and the desired value written to the file to tune. I saw that this RFC asks about whether debugfs is an appropriate interface for the *tracing* capability of the platform. Have similar questions been raised about the tuning interfaces? It looks to me like tuning could be handled entirely using sysfs attributes. I think trying to handle these mostly decoupled feature in the same place is likely to be a mistake. Daniel.