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From: Rob Herring <robh@kernel.org>
To: Lucas Stach <l.stach@pengutronix.de>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Richard Zhu <hongxing.zhu@nxp.com>,
	NXP Linux Team <linux-imx@nxp.com>,
	linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	kernel@pengutronix.de, patchwork-lst@pengutronix.de
Subject: Re: [PATCH 4/7] dt-bindings: imx6q-pcie: add a property configure refclk pad usage mode
Date: Tue, 11 May 2021 14:55:52 -0500	[thread overview]
Message-ID: <20210511195552.GA2496435@robh.at.kernel.org> (raw)
In-Reply-To: <20210510141509.929120-4-l.stach@pengutronix.de>

On Mon, May 10, 2021 at 04:15:06PM +0200, Lucas Stach wrote:
> Starting with the i.MX7, arch PCIe instance has a differential refclk pad,
> which can beused in multiple ways:
> 
> - It's not used at all and the PHY reference clock is provided by a SoC
>   internal source, like on the previous SOCs.
> - It's used as a clock input, for the board to provide a reference clock
>   for the PHY.
> - It's used as a clock output, where the PHY reference clock is provided
>   by a SoC internal source and the same clock is also routed to the
>   refclk pad for consumption of board-level components.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> index 308540df99ef..3ebd8553a818 100644
> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> @@ -38,6 +38,11 @@ Optional properties:
>    The regulator will be enabled when initializing the PCIe host and
>    disabled either as part of the init process or when shutting down the
>    host.
> +- fsl,refclk-pad-mode: Usage mode of the refclk pad. Valid values:
> +  - 0: pad not used. PHY refclock is derived from SoC internal source.
> +  - 1: pad input. PHY refclock is provided externally via the refclk pad.
> +  - 2: pad output. PHY refclock is derived from SoC internal source and
> +       provided on the refclk pad.

Seems like this belongs in the PHY's node?

Or you could determine this based on the PHY's clock source. At least 
for the first 2 cases. Is there a known user for the 3rd case? If so, 
it's possible that what it's connected to needs a clock provider as 
well.

Rob

  reply	other threads:[~2021-05-12 21:09 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-10 14:15 [PATCH 1/7] PCI: imx6: Move i.MX8MQ controller instance check to correct case statement Lucas Stach
2021-05-10 14:15 ` [PATCH 2/7] PCI: imx6: Initialize ATU unroll offset Lucas Stach
2021-05-11 20:03   ` Rob Herring
2021-05-10 14:15 ` [PATCH 3/7] PCI: imx6: Rework PHY search and mapping Lucas Stach
2021-05-10 17:05   ` Rob Herring
2021-05-11  8:11     ` Lucas Stach
2021-05-11 14:21       ` Rob Herring
2021-05-11 14:54         ` Lucas Stach
2021-05-11 15:22           ` Rob Herring
2021-08-04 11:55           ` Lorenzo Pieralisi
2021-05-10 14:15 ` [PATCH 4/7] dt-bindings: imx6q-pcie: add a property configure refclk pad usage mode Lucas Stach
2021-05-11 19:55   ` Rob Herring [this message]
2021-05-10 14:15 ` [PATCH 5/7] PCI: imx6: Configure PHY refclock according to DT property Lucas Stach
2021-05-10 14:15 ` [PATCH 6/7] dt-bindings: imx6q-pcie: add compatibles for i.MX8MM PCIe Lucas Stach
2021-05-10 14:15 ` [PATCH 7/7] PCI: imx6: Add i.MX8MM support Lucas Stach
2021-06-23 13:46 ` [PATCH 1/7] PCI: imx6: Move i.MX8MQ controller instance check to correct case statement Lorenzo Pieralisi

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