Re: [PATCH 3/5] PCI: Improve the mrrs quirk for LS7A

[Bjorn Helgaas <helgaas@kernel.org>]

On Fri, May 14, 2021 at 04:00:23PM +0800, Huacai Chen wrote:
> In new revision of LS7A, some pcie ports support larger value than 256,
> but their mrrs values are not dectectable. And moreover, the current
> loongson_mrrs_quirk() cannot avoid devices increasing its mrrs after
> pci_enable_device(). So the only possible way is configure mrrs of all
> devices in BIOS, and add a pci dev flag (PCI_DEV_FLAGS_NO_INCREASE_MRRS)
> to stop the increasing mrrs operations.

s/mrrs/MRRS/
s/dectectable/detectable/

This doesn't make sense to me.  MRRS "sets the maximum Read Request
size for the Function as a Requester" (PCIe r5.0, sec 7.5.3.4).

The MRRS in the Device Control register is a 3-bit RW field (or a RO
field with value 000b).  If it's RW, software is allowed to write any
3-bit value to it.  There is no "maximum allowed value" for software
to detect.

The value software writes is only a *limit* on the Read Request size.
The hardware is never obligated to generate Read Requests of that max
size.  If software writes 101b (4096 byte max size), and the hardware
only supports generating 128-byte Read Requests, there's no issue.
It's perfectly fine for the hardware to generate 128-byte requests.

Apparently something bad happens if software writes something "too
large" to MRRS?  What actually happens?

If the problem is that the device generates a large Read Request and
in response, it receives a data TLP that is larger than it can handle,
that sounds like an MPS issue, not an MRRS issue.

Based on the existing loongson_mrrs_quirk(), it looks like this is a
long-standing issue.  I'm sorry I missed this when reviewing the
driver in the first place.  This all needs a much better explanation
of what the real problem is.  The "h/w limitation of 256 bytes maximum
read request size" comment just doesn't make sense from the spec point
of view.

I do know that Linux uses MRRS and MPS in ... highly unusual ways, and
maybe we're tripping over that somehow.  If so, we need to figure out
exactly how so we can make Linux's use of MPS and MRRS better overall.

> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
> ---
>  drivers/pci/pci.c    | 5 +++++
>  drivers/pci/quirks.c | 6 ++++++
>  include/linux/pci.h  | 2 ++
>  3 files changed, 13 insertions(+)
> 
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index b717680377a9..6f0d2f5b6f30 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -5802,6 +5802,11 @@ int pcie_set_readrq(struct pci_dev *dev, int rq)
>  
>  	v = (ffs(rq) - 8) << 12;
>  
> +	if (dev->dev_flags & PCI_DEV_FLAGS_NO_INCREASE_MRRS) {
> +		if (rq > pcie_get_readrq(dev))
> +			return -EINVAL;
> +	}
> +
>  	ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
>  						  PCI_EXP_DEVCTL_READRQ, v);
>  
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index 66e4bea69431..10b3b2057940 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -264,6 +264,12 @@ static void loongson_mrrs_quirk(struct pci_dev *dev)
>  		 * any devices attached under these ports.
>  		 */
>  		if (pci_match_id(bridge_devids, bridge)) {
> +			dev->dev_flags |= PCI_DEV_FLAGS_NO_INCREASE_MRRS;
> +
> +			if (pcie_bus_config == PCIE_BUS_DEFAULT ||
> +			    pcie_bus_config == PCIE_BUS_TUNE_OFF)
> +				break;
> +
>  			if (pcie_get_readrq(dev) > 256) {
>  				pci_info(dev, "limiting MRRS to 256\n");
>  				pcie_set_readrq(dev, 256);
> diff --git a/include/linux/pci.h b/include/linux/pci.h
> index c20211e59a57..7fb2072a83b8 100644
> --- a/include/linux/pci.h
> +++ b/include/linux/pci.h
> @@ -227,6 +227,8 @@ enum pci_dev_flags {
>  	PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
>  	/* Don't use Relaxed Ordering for TLPs directed at this device */
>  	PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
> +	/* Don't increase BIOS's MRRS configuration */
> +	PCI_DEV_FLAGS_NO_INCREASE_MRRS = (__force pci_dev_flags_t) (1 << 12),
>  };
>  
>  enum pci_irq_reroute_variant {
> -- 
> 2.27.0
>