From: Om Prakash Singh <omp@nvidia.com>
To: <vidyas@nvidia.com>, <lorenzo.pieralisi@arm.com>,
<bhelgaas@google.com>, <thierry.reding@gmail.com>,
<jonathanh@nvidia.com>
Cc: <linux-tegra@vger.kernel.org>, <linux-pci@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <kthota@nvidia.com>,
<mmaddireddy@nvidia.com>, Om Prakash Singh <omp@nvidia.com>
Subject: [PATCH V1 1/5] PCI: tegra: Fix handling BME_CHGED event
Date: Thu, 27 May 2021 13:16:10 +0530 [thread overview]
Message-ID: <20210527074614.49149-4-omp@nvidia.com> (raw)
In-Reply-To: <20210527074614.49149-1-omp@nvidia.com>
In tegra_pcie_ep_hard_irq(), APPL_INTR_STATUS_L0 is stored in val and again
APPL_INTR_STATUS_L1_0_0 is also stored in val. So when execution reaches
"if (val & APPL_INTR_STATUS_L0_PCI_CMD_EN_INT)", val is not correct.
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
---
drivers/pci/controller/dwc/pcie-tegra194.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index bafd2c6ab3c2..c51d666c9d87 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -615,10 +615,10 @@ static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg)
struct tegra_pcie_dw *pcie = arg;
struct dw_pcie_ep *ep = &pcie->pci.ep;
int spurious = 1;
- u32 val, tmp;
+ u32 val_l0, val, tmp;
- val = appl_readl(pcie, APPL_INTR_STATUS_L0);
- if (val & APPL_INTR_STATUS_L0_LINK_STATE_INT) {
+ val_l0 = appl_readl(pcie, APPL_INTR_STATUS_L0);
+ if (val_l0 & APPL_INTR_STATUS_L0_LINK_STATE_INT) {
val = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0);
appl_writel(pcie, val, APPL_INTR_STATUS_L1_0_0);
@@ -636,7 +636,7 @@ static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg)
spurious = 0;
}
- if (val & APPL_INTR_STATUS_L0_PCI_CMD_EN_INT) {
+ if (val_l0 & APPL_INTR_STATUS_L0_PCI_CMD_EN_INT) {
val = appl_readl(pcie, APPL_INTR_STATUS_L1_15);
appl_writel(pcie, val, APPL_INTR_STATUS_L1_15);
@@ -648,8 +648,8 @@ static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg)
if (spurious) {
dev_warn(pcie->dev, "Random interrupt (STATUS = 0x%08X)\n",
- val);
- appl_writel(pcie, val, APPL_INTR_STATUS_L0);
+ val_l0);
+ appl_writel(pcie, val_l0, APPL_INTR_STATUS_L0);
}
return IRQ_HANDLED;
--
2.17.1
next prev parent reply other threads:[~2021-05-27 7:46 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-27 7:46 [PATCH V1 0/6] Update pcie-tegra194 driver Om Prakash Singh
2021-05-27 7:46 ` [PATCH V1 0/5] " Om Prakash Singh
2021-05-27 7:46 ` [PATCH] PCI: tegra: Cleanup unused code Om Prakash Singh
2021-05-27 7:46 ` Om Prakash Singh [this message]
2021-05-27 7:46 ` [PATCH V1 2/5] PCI: tegra: Fix MSI-X programming Om Prakash Singh
2021-05-27 7:46 ` [PATCH V1 3/5] PCI: tegra: Disable interrupts before entering L2 Om Prakash Singh
2021-05-27 7:46 ` [PATCH V1 4/5] PCI: tegra: Don't allow suspend when Tegra PCIe is in EP mode Om Prakash Singh
2021-05-27 7:46 ` [PATCH V1 5/5] PCI: tegra: Cleanup unused code Om Prakash Singh
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